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RISC-V (featuring SiFive HiFive)

The RISC-V Instruction Set Open Standard Architecture

Vincent Tabora
Dec 14, 2020 · 6 min read

Open architectures foster innovation because of the material is available with no royalty. Developers can adopt it as a standard for software and hardware specifications. The Open Source community has benefited tremendously from this when it comes to software development. On the hardware side, an open standard should also help developers build their own systems and solutions. All that developers will need are the instruction set to the hardware and they can build on top of it.

The RISC-V open standard ISA (Instruction Set Architecture) was developed by 325 companies (now up to 500 members) to come up with a system for building on top of processors. It is now run by a foundation that maintains the standard. The instruction sets are supported by vendors who develop compatible hardware. This creates a system design that allows software engineers to program code in firmware that is supported across a wide variety of devices that support RISC-V instruction sets.

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Three of the inventors of the RISC-V ISA (Source RISC-V)

Purpose

The cost of development can run high. In developing closed architecture and proprietary systems, the developers can protect their trade secrets but the problem comes to integration. Such systems limit their market reach, unless they are the only producer. In that case it would be monopolistic and without other developers to compete with, there is little innovation in the products. These systems can also be very expensive for other developers to adopt as a standard. They would require licensing and royalty fees in order to be used by other companies. It is centralized and tightly controlled by the company who owns the rights and patents to the technology.

Open source solutions offer more space for developers to enter and innovate on products. They are not constrained by the intellectual property rights of the inventor. With the RISC-V, developers can follow a standard set of protocols for product development. It also fosters community since there are less barriers to entry. Developers of all types from different companies and industries can share the same space and collaborate in research and development. This results in a more organized way of building systems that is not restricted by a single entity.

According to one of the inventors of RISC-V, David Patterson (Google Distinguished Engineer):

“ … the original motivation was to experiment more with chip design because Moore’s Law, the prediction that the number of transistors on a chip doubles every couple of years, was slowing down.”

RISC system design (on which RISC-V is based) is also more energy efficient and optimizes instruction execution much better than its competing architecture on the x86 platform (e.g. Intel and AMD). This allows better battery life on devices due to lower power consumption and faster execution of operations for certain instructions to the CPU.

Architecture

RISC-V supports both 32-bit, 64-bit and 128-bit instruction sets. It is based on the RISC (Reduced Instruction Set Computer) architecture, which emphasizes instruction optimization rather than specialized instruction sets. RISC-based systems allow a process to complete much faster by removing the complexity in the execution pipeline of the instruction set.

The developers of RISC-V (UC Berkeley) had the following goals in mind when they set out with the project:

RISC-V uses standard naming conventions for their instruction sets. The name format is:

RV[###][abc…..xyz]

RV — Indicates the RISC-V architecture.

[###] — Indicate the width of the integer register file and the size of the user address space.

[abc…xyz] — Indicates the set of extensions supported by an implementation.

The RISC-V uses three privileged modes as defined in their Privileged Specifications. These are:

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The RISC-V instruction set architecture

The RISC-V has 32 (or 16 in the embedded variant) integer registers. When the floating-point extension is implemented, it has a separate 32 floating-point registers. The instructions address only registers.

The first integer register is a 0 register, and the remainder are general-purpose registers. Using a zero register makes for a simpler instruction set. For example:

move rx to ry 
becomes
add r0 to rx and store in ry.

User-mode programs can access only those used for performance measurement and floating-point management. There are no instructions that exist for saving and restoring multiple registers. It was considered too complex and slows down operations.

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Register names with descriptions (Source Wikipedia)
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Register organization in RISC-V

Here are the main advantages of RISC-V’s architecture (From Electronics Hub):

Applications

Hare some companies that have used the RISC-V in their products:

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SweRV Core (Source Western Digital)
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The PolarFire Architecture (Source Microchip)

According to Junho Huh (Research VP Samsung Electronics):

“It was a risk to use RISC-V, but the company expects to introduce RISC-V across a large number of products in the future, including AI, security, and safety chips.”

Conclusion

The RISC-V defines a commercial product design for general to more application specific computing. Such open standard architecture brings together a community of innovators that can build and foster further developments in the design. Its closest competitor, in terms of architecture, is ARM. The main difference is that ARM does not provide their instruction set royalty free. ARM licenses its instruction set to companies like Qualcomm and Apple, while RISC-V is free-to-use and does not require any royalty fees. This is ideal for startups that have new ideas but want to get started building on something with a minimal budget.

Such developments in open standards for processor design will surely usher in more players in the space. It is already being embraced by larger companies, including Samsung. Its application in IoT, mobiles and industrial instruments is as lucrative as the retail market for personal computers. The standards will also remain under continuous development since it does not require the constraints of a paid development team. You have liked minded individuals working as a group to benefit all. The community is coming together in the project with more contributions coming in since there are minimum barriers to entry.

References:

  1. An Introduction to the RISC-V Architecture
  2. RISC vs CISC

0xMachina

Essays and articles about interacting with modern devices…

Vincent Tabora

Written by

Editor HD-PRO, DevOps Trusterras (Cybersecurity, Blockchain, Software Development, Engineering, Photography, Technology)

0xMachina

0xMachina

Essays and articles about interacting with modern devices and how they work.

Vincent Tabora

Written by

Editor HD-PRO, DevOps Trusterras (Cybersecurity, Blockchain, Software Development, Engineering, Photography, Technology)

0xMachina

0xMachina

Essays and articles about interacting with modern devices and how they work.

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