3D IC Technology

A 3D IC composed of two or more layers of active electronic components, integrated both horizontally and vertically.

what is motivation behind 3D IC technology?

Basically, interconnect structures increasingly consume more of the facility and delay budgets in modern design so there’s solution for this i.e to extend the number of nearest neighbour seen by each transistor by using our 3D IC techniques. Smaller wire cross-sections smaller wire pitch and longer lines to traverse larger chips may increase in RC delays so RC delay is increasingly becoming the dominant factor. At 250 nm Cu was introduced alleviate the adverse effect of skyrocketing interconnect delay.130 nanometer technology node, substantial interconnect delays will result.

Why 3D-IC?

So why we want to use 3D-IC techniques as it reduces the space wastage on the substrate. Also it improves interconnections among different wafers, to reduce length of interconnections which will also reduce heat dissipation and RC delays. Also 3D IC can accommodate homogeneous as well as heterogeneous chips. This motivated researchers to switch to 3D IC’s from 2D.

Manufacturing Processes

Monolithic:
A technology breakthrough allows the fabrication of semiconductor with multiple thin tiers of copper-connected active devices utilizing conventional fab equipment. Electronic components and their connections are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning ,thinning, bonding or TSV.

Wafer to wafer:

It is a way to built electronic components on two or more semiconductor wafers that are then aligned, bonded and then diced into 3D ICs. Verticle connections can be stacked after bonding but, they are preferably built into the wafer before boding. Wafer can be thinned before or after bonding.

Die to wafer:

Electronic components are built on two semiconductor wafers. One wafer
is diced; the singulated dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional die may be added to the stacks before dicing.

Die to die:

Electronic components are built on multiple die, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding . One advantage of die-to-die is that each component die can be tested first , so that one bad die does not run an entire stack. Moreover each die in the 3D IC can be binned beforehand , so that they can be mixed and marched to optimize power consumption and performance.