3D-IC Technology and Reliability Challenges
Three-dimensional (3D) ICs using TSVs are the most promising candidate for high performance and low power computing. They have lots of advantages such as short wiring length, small chip size, and small pin capacitances. There are millions of TSVs and metal micro bumps in vertically stacked thinned Si chips. This article focuses on the most potent reliability issues such as Cu contamination and thermomechanical stress.
- Cu diffusion from the backside and TSV
Cu diffusion is one of the most important reliability issues. Cu acts as a life time killer in the Si substrate. Cu diffuses from the wafer/chip backside and Cu-TSV in stacked thinned Si wafers/chips. A C-t method using planar and trench MOS capacitors with Cu/Ta gate electrodes can effectively test such Cu diffusion. In the case of Cu contamination from TSV, the Bosch process was used to fabricate two forms of trench MOS capacitors with sidewall scalloping and average roughness of 30 and 200 nm to compare the influence of the phase coverage of the barrier layer. After sputtering a 100-nm-thick oxide liner into through holes, Ta films with surface thicknesses of 10 and 100nm were formed as a barrier layer. C-t curves of MOS capacitors with 10nm-thick-Ta film indicated significant degradation after 5-min annealing, especially with sidewall roughness of 200 nm. This means Cu atoms diffused into device regions from the Cu TSVs through scallop portions.
2. Mechanical stress by TSV and micro bump
Mechanical stress distributions induced by TSVs and metal micro bumps can be precisely evaluated with 2D u-RS. It was clearly shown that the compressive stress propagated horizontally from the micro bump regions to the adjacent regions. The stress distributions were very complicated and changed accordingly with both micro bump design and bonding process conditions. 3D-ICs are strongly required to optimize fabrication process and circuit layout including TSV and micro bump stress distributions.
3. Mechanical stress evaluation with DRAM cell array
Data retention variance is one of the most important 3D-DRAM reliability problems. The modulation of electron numbers in the storage capacitor caused by local mechanical stress in the 3D chip stacking phase is responsible for this variation. A DRAM chip with NMOS transistors and planar-type MOS capacitors was used as a memory cell to test the effects of local stress on memory retention characteristics.
Several reliability issues still exist in 3D-ICs caused by lots of TSVs and micro bumps. Cu contamination and thermomechanical stress were evaluated by new methods. It was found that the mechanical stress distributions induced around micro bump joining were very complicated. Using these evaluation methods, design guidelines for 3D ICs can be optimized and highly reliable 3DICs will be successfully fabricated.
