Architecture of 3 Dimensional Integrated Circuits
The semiconductor industry has made tremendous improvements in the performance, power, and cost of integrated circuits (ICs) over the last five decades . For the first few decades in the late 1960s after the digital revolution started, the semiconductor industry improved in areas like performance, power, and area in accordance with Moore’s law. However, as the device dimensions started reducing and the demand for performance increasing, traditional scaling was not enough to keep up with Moore’s law.
3D integration provides an elegant solution to the off-chip interconnect problem by bringing the communicating ICs physically closer to each other, while simultaneously reducing the area footprint, which is critically important for handheld devices. Hence, 3D integration is considered to be a promising technology to alleviate the off-chip interconnect problem.
The most commonly studied architectures for 3D ICs are:
A. Silicon interposer (2.5D) : Since technically 3D architecture is not a true , silicon interposer provides some advantages over conventional packages. 1.very fine pitch wires, similar to on-chip BEOL interconnects can be patterned on silicon interposers. 2. Due to the matched coefficient of thermal expansion between the chip and silicon interposer, reliable fine pitch micro-bumps can be used as first level interconnect. As a result, silicon interposers offer a significant bandwidth and energy improvement over conventional off-chip interconnects.
B. Stacked Memory : Multiple DRAM die are stacked on top of each other, with one logic die at the bottom for control. The memory stack significantly increases the capacity that can be fit in a given area, whereas the logic die handles communication with other ICs on the interposer. The two prominent memory architectures for stacked memory are High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC) from Micron.
C. Memory on Processor : The ability to stack high density DRAM on top of the processor is extremely valuable for some of the applications. By reducing the physical distance between the two communicating ICs, the losses in the chip-to-chip link can be reduced. Additionally, since Through Silicon Vias (TSVs) can be densely packed to provide a large bus width, the data rate for operation can be reduced significantly compared to the conventional IO links that typically operate at tens of GHz. This, in turn simplifies the IO circuits considerably and minimizes the issues that creep up at higher frequencies.
D. Logic on Logic : The motivation for stacking logic on logic is to reduce the aggregate interconnect length in a large logic circuit. For example, if a large 2D chip like a microprocessor is 2cm x 2cm in dimensions, the overall interconnect length can be reduced significantly if the microprocessor is partitioned into 4 blocks of 1cm x 1cm stacked on top of each other and connected with TSVs. However, the caveat here is that the communication between the 4 partitions should be limited.
E. Heterogeneous Integration : This is the ultimate holy grail of researchers seeking to integrate multiple technologies stacked together in a single package. The dream is to one day combine logic, memory, RF, sensor ICs built separately in the optimal technology within a package. There are several advantages to such a heterogeneous 3D IC including cost, form factor, performance, IO count reduction, and lower power consumption.
