Fan-out Wafer Level Packaging of 3 Dimensional Integrated Circuits.

Advances in packaging have afforded companies the flexibleness to position an outsized number of contacts in smaller footprints, Improve the thermal characteristics and improve the electrical performance of their system. one of these advances comes within the type of (FOWLP) Fan-out wafer-level packaging. Fan-out wafer is also known as microcircuit packaging technology, with an improvement in wafer level packaging(WLP) solutions. In conventional technologies, a wafer is diced first, so individual dies are packaged; package size is sometimes considerably larger than the die size. against this, in standard WLP flows integrated circuits are packaged while still a part of the wafer, and thus the wafer (with outer layers of packaging already attached) is diced afterwards; the size of resulting package is identical to size of dice. However, the advantage of getting atiny low low package comes with a downside of limiting the amount of external contacts which may be accommodated within the limited package footprint; this might become a big limitation when complex semiconductor devices requiring an oversized number of contacts are considered. Fan-out WLP was developed to relax that limitation. It provides a smaller package of footprint together with improvement in thermal and electrical performances. In fan-out WLP the wafer is diced first, and again the dies are very precisely re-positioned on a carrier wafer or panel, with space for fan-out kept around each die. The carrier is constructed by molding, followed by redistribution layer at top of the molded area and resulting in formation of solder balls on top.