Reducing Test Time for 3D-ICs by Improved Utilization of Test Elevator.

A three-dimensional integrated circuit. As we know it is metal-oxide semiconductor. It is manufactured by stacking silicon. It is usually interconnecting them by using vertically. So, it is behaving like single device. There are many advantages but 3d-ic mostly used in the reducing test time and improve the utilization of test elevator. A highly efficient test compression scheme for 3D-IC is proposed. It is a new technology that provide a number of significant advantages that it increased functional density, interconnection is shorter and low power. For reducing the time the test compression is the main process so it is all over based on the core design where each core has its own decompressor operating independently of the other core decompressor. In that the input data bandwidth from the automatic test equipment is distributed to core decompression using TAM.
Test Architecture of 3D-ICs with Static Allocation of Tester Channels: -In that the test channel allocation is static. In order to make it dynamic, it is necessary to route the entire ATE bandwidth to all the layers, and control the number of channels.
Proposed Architecture with Daisy-Chained Decompressors: — In that the number of channels between layer 2 and layer 3 is less than the number of channels between layer 1 and layer 2, which in turn is less than the input bandwidth to the decompressor in layer 1. Basically, it provides some flexibility in encoding the test cubes. Free variables unused while encoding a core in a layer are available to encode other cores in the layers above, so its improving encoding efficiency.
Optimizing Number of Test Elevators by Inter-layer Serialization of Test Data: — In this process an implementation is proposed using a serializer-reserialize structure to further reduce the number of test elevators required to implement the proposed architecture. The functional frequency is greater than the shift frequency, since the scan clock tree is generally not buffered up for high speeds. It causes the causes a voltage drop in the power lines. To reduce these problems, functional; frequency is greater than the scan frequency or we can say higher than scan frequency. Using this process of proposed implementation, the difference between the slower scan shift frequency and the faster functional frequency can be exploited to further reduce the number of test elevators.