Know what you’re printing: the story of YieldStar

In the semiconductor world, success comes from creating faster, lower-power chips that have more functionality. That in turn means being able to print ever more complicated patterns built up from smaller and smaller features onto a silicon wafer — and being able to do that reliably enough to ensure high yields.

An illustration of an ASML scanner (left) and the track with an integrated YieldStar metrology system (right). Imaging , material processes (coating, baking, rinsing, and developing) and wafer metrology come together in one production flow.

In today’s most advanced chips, those features could be as small as 10 nanometers. “At this scale, complicated chip patterns are split into two or more simpler patterns that are printed separately, and then combined to make the desired pattern on the wafer. This is called multiple patterning,” explains Chris Kim, Product Manager at ASML.

Corrections to nanometer accuracy

This multiple patterning presents a challenge to control the lithographic process used to create chips. Factors such as how well you can align two patterns (overlay) and how consistently you can reproduce the size of features (critical dimension uniformity or CDU) become crucial to achieving smaller features. Meanwhile, tight focus control is required to ensure the features have the right shape — essential for high yields at these tiny scales.

Margins are extremely small. Any variation in these three parameters needs to be corrected to nanometer accuracy. In the multistep process used to transfer patterns to silicon, manufacturers would previously optimize each process step individually (such as exposing, etching, or chemical-mechanical planarization) to ensure production performance. But that is no longer enough. Instead, manufacturers are using flexibility in one step to correct for error footprints arising in other steps. To apply such corrections, you need to know exactly what you are correcting for. You have to measure what you’re printing.

Knowing what you’re printing

Manufacturers had been measuring features on printed wafers for years, but back in 2008, there was a plenty of room for improvement. For example, wafers could only be inspected by interrupting them from their automated flow through the fab. With high productivity and small margins for error top-of-mind for chipmakers, the idea for a more holistic approach to lithography was born. Metrology and computational modeling became as important as the scanner itself.

To apply corrections to the lithography process, you have to measure what you’re printing. At these tiny scales, typical defects like a ‘mouse bite’ or ‘bridge’ can be detrimental to the functioning of a chip.

ASML began developing its own, diffraction-based approach to metrology. This approach allowed measurements to be carried out much faster without compromising accuracy. The result was YieldStar: a single wafer metrology system that could measure overlay, CDU and focus control.

YieldStar 350E (illustration)

“YieldStar was a game changer in wafer metrology. With its fast yet accurate diffraction-based measurements, it allowed metrology to be embedded into the production line for the first time. This meant sample wafers could be measured, and corrections calculated and fed back to the scanner in time for processing later wafers,” Kim adds.

By intelligently integrating of lithography, metrology and advanced computational modeling, the holistic lithography vision could extend the capabilities of scanners in the fab.

Hardware and software that change the game

ASML has recently released the next generation metrology system: the YieldStar 350E. Built for the more exacting demands of today’s multiple patterning lithography, it generates 40% more metrology data than its predecessor — and that can even go up to 70% more data for the most advanced and complex 10 nm logic node, which will start to ramp in 2016. And, because the YieldStar 350E measures as fast as our most advanced lithography scanners can print, it is the first metrology system that allows chipmakers to measure every single wafer at full production throughput.

These measurements are fed into a software suite called LithoInsight, which translates the huge amount of raw metrology data into informative visualizations of parameters such as overlay, focus control and critical dimension uniformity. The suite has an intuitive, application-centered interface that engineers in the fab or even remotely can use to optimize the manufacturing process.

The YieldStar 350E’s capabilities stem from key innovations such as a new, dedicated sensor for overlay measurements. In addition, improvements to how the light used in the diffraction-based measurements is both delivered and collected allows the new system to carry out multiple measurements at the same time. By increasing the number of sampling points, the YieldStar 350E actually helps reduce the amount manufacturers need to invest in metrology to deliver high yields.

“The YieldStar 350E will take a leading role in holistic lithography, allowing chipmakers in all areas of the semiconductor industry continue the drive for more advanced ICs,” Kim concludes.