San Diego, California | Telecommunications Industry
We are seeking a DFT Engineer for a very important client.
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The DDR Design Team is currently seeking candidates for a senior position responsible for the implementation of advanced DFT/DFD(design for test/design for debug) techniques for low power, high performance on high-speed DDR PHY systems. The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning.
Deployment and implementation of advanced DFT/DFD(design for test/design for debug) techniques for low power and high performance. Deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning.
The ideal candidate will possess the following skills:
- Strong fundamental knowledge of DFT/DFD techniques
- Understanding of core-based test methodology and scan isolation
- Knowledge in fault modeling Stuck-at, Transition Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models
- Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing
- Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Mentor Fastscan ATPG tools and Synopsys DFTC scan insertion
- Experience in Logic Design, Verilog RTL, verification, and static timing analysis
- Working knowledge in two or more of the following; Verilog, TCL or Perl
- Experience with industry simulation tools such as VCS, Modelsim, or others
- Direct experience in silicon bring-up, debug, and validation of DFT features on ATE
- Detail oriented with strong organizational, problem solving and communication skills
- Experience with formal verification tools such Verplex, Formality, etc.
- Knowledge and experience of timing closure and industry tools like PrimeTime and PTSI
Required: Bachelor’s, Computer Engineering
Preferred: Master’s, Computer Engineering or equivalent experience