High-Speed Analog & Mixed-Signal PLL Design Engineer

San Diego, California | Telecommunications Industry

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We are seeking a High-Speed Analog & Mixed-Signal PLL Design Engineer for a very important client.

The Mixed-Signal design team is actively looking for a mid to senior-level analog and mixed-signal circuit designer to work on SerDes PHY designs. This designer will be involved in delivering next-generation PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-edge CMOS process technology nodes at 28nm and beyond. Design goals also include low-power analog designs to address low-power wireless products.

The primary responsibility of this position entails working within a team to deliver analog and mixed-signal transistor level circuit designs, circuit architectures, simulation results, and silicon characterization for high-speed, low-power PHY SerDes blocks, PLL design experience preferably for high-speed SerDes and DDR PHY applications, Analog and or Digital PLLs for frequency synthesis and/or SerDes applications

The ideal candidate will possess the following qualifications:

- Understanding of PLL Loop Dynamics and Building blocks

- Understanding of PLL Jitter sources and modeling (RJ & DJ)

- Design of several of PLL blocks like charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers

Education:

Required: Bachelor’s, Computer Engineering and/or Electrical Engineering

Preferred: Master’s, Computer Engineering or equivalent experience