Your Ultimate and Comprehensive Guide to

SLACK, SKEW, and SLEW in VLSI

The Three Musketeers of Timing ⏱️

14 min readSep 3, 2024

You know what they say: Timing is everything. If it’s meant to happen, it will, at the right time, for the right reasons, blah blah blah… But in the hands of a skilled VLSI Physical Design Engineer, perfect timing is not just a possibility; it’s a guarantee. YES, EVERY SINGLE TIME!!!

Hello Peeps! How you doin’? 😏 If you like your chips crisp, whether they’re the salty snack variety or the silicon kind, you’re in the right place! If you have ever voyaged through the ocean of VLSI, you’ve probably already bumped into the infamous three musketeers of timing in your circuits: SLACK, SKEW, and SLEW. While they might sound and mean the same to a noob in VLSI, only the PRO-OGs know the difference between the three! So, grab your favourite bag of chips (the edible ones, DUH!), and let’s swoop into what makes this trio so essential in making your design an absolute delight!

Now, the motive behind this blog — This might just be the only blog that clearly explains the difference between these three similar-sounding terms: Slack, Skew, and Slew, which are often confused by VLSI freshers. When I first started learning Static Timing Analysis (STA) during Physical Design (PD), I found these terms incredibly confusing. I set out to find a reliable resource that explained the difference between these homophones all in one place, but to my disappointment, I couldn’t find one. Most resources either covered one term individually or explained two but left out the third.

So, after thoroughly understanding these concepts myself, I decided to write this blog to help others like me so you don’t have to go through the same confusion I did!

As mentioned above, this is something related to STA — Static Timing Analysis, an important and inevitable step of the VLSI Design Flow, precisely speaking, the Backend or the Physical Design (PD).

1. SLACK

SLACK is the difference between the desired or required arrival time (RAT) and the achieved or actual arrival time (AAT) of a signal at a node in the circuit. Required arrival time (RAT) is the latest time a signal can arrive at a node without violating the timing constraints. In contrast, actual arrival time (AAT) is the actual time that a signal arrives at a node based on the design delays. Slack can be positive, negative, or zero.

Slack comes in two flavours. Based on calculating either the SETUP Slack (for the worst delay path) or the HOLD Slack (for the best delay path), we can have two formulas for calculating Slack:

Setup Slack = Required Arrival Time (RAT) — Actual Arrival Time (AAT)

Hold Slack = Actual Arrival Time (AAT) — Required Arrival Time (RAT)

Positive Slack means the design is working according to the specifications and has some more margin as well.
Zero Slack means the design is critically working at the desired specifications and has no timing margin.
Negative Slack means the design has not achieved the specified timing and has a timing violation.

Let’s look at one example of Register to Register Timing Slack Analysis. It can also be called a flip-flop to flip-flop analysis. There are mainly four types of paths for timing analysis. These are:

Input to Output
Input to Register
Register to Output
Register to Register

But, to keep things easily understandable and simple, here we have taken the example of Register to Register (flip-flop to flip-flop) Timing Analysis to start with.

Register to Register circuit having a Launch flop and a Capture flop connected via a combinational logic

Propagation Delay for each combinational element

Setup, Hold and Clock-to-Q delay of both the flops

Here, UFF1 is called the Launch Flop (or source flop) because it launches/produces the data, and UFF3 is called the Capture Flop (or destination flop) because it captures the data that is launched by the Launch Flop. This is just some fancy English.

Clock-to-Q delay [Tclk→q]: After detecting the clock edge, the flip-flop needs some time to process the input data and propagate the correct output. This time interval is known as the clock-to-Q delay (Tclk→q). It simply refers to the time it takes for the flip-flop’s output (Q) to change state after the clock signal has triggered a transition.

The delay calculations for Path 1 and Path 2 are given below.

Delay in Path 1 = Tpropogation(UOR4)+ Tpropogation(UNAND6) = 5ns + 6ns = 11ns
Delay in Path 2 = Tpropogation(UNAND0) + Tpropogation(UBUF2) + Tpropogation(UOR2) + Tpropogation(UNAND6) = 6ns + 2ns + 5ns + 6ns = 19ns

Hence, Path 2 is the longest path and has the highest or worst delay and Path 1 is the smallest path and has the least or best delay.

Register-to-Register Setup Slack

The worst delay or maximum delay path is chosen for setup analysis. Here it is, Path 2.

Here, assuming the clock period (Tclk) = 30ns,

Actual Arrival Time = Tclk→q(UFF1) + Tpropogation(UNAND0) + Tpropogation(UBUF2) + Tpropogation(UOR2) + Tpropogation(UNAND6) = 3ns + 19ns = 22ns

Required Arrival Time = Tclk — Tsetup(UFF3) = 30ns — 3ns = 27ns

Setup Slack = Required Arrival Time — Actual Arrival Time = 27ns — 22ns = +5ns (Positive)

Here, as the Setup Slack value is positive, there is no setup timing violation!

The negative value of Setup Slack means that the data arrives late within the setup time window, which violates the setup time requirement.

Register-to-Register Hold Slack

The best delay or minimum delay path is chosen for hold analysis. Here it is, Path 1.

Here, assuming the same clock period, i.e., Tclk = 30ns,

Actual Arrival Time = Tclk→q(UFF1) + Tpropogation(UOR4) + Tpropogation(UNAND6) = 3ns + 11ns = 14ns

Required Arrival Time = Thold(UFF3) = 2.5ns

Hold Slack = Actual Arrival Time — Required Arrival Time = 14ns — 2.5ns = +11.5ns (Positive)

Here, as the Hold Slack value is positive, there is no hold timing violation!

The negative value of Hold Slack means that the signal value propagates from one register to the next too fast, which violates the hold time requirement.

The most common hold time fix is to add buffers between registers, which increases the combinational logic delay for meeting hold time constraints.

It is interesting to note that the clock frequency doesn’t affect the Hold time or the Hold Slack, so it is critical to fix the hold time violations in a design before addressing the setup violations if both exist simultaneously!

How to Mitigate Slack?

Several techniques can be used, such as sizing, buffering, and re-timing.

Sizing involves changing the size (particularly the width) of transistors to adjust their drive strength and delay.
Buffering involves inserting buffers or inverters to boost signal strength and reduce delay.
Re-timing is a technique where flip-flops or registers are relocated within the design.

All of these techniques can be done manually or automatically using design tools. Ultimately, these techniques can balance the slack distribution, improve the slack of long interconnects and fanout nodes, reduce loading effects, and optimise setup and hold times.

Data Path and Clock Path in Slack Analysis (Additional Reading)

Data Path and Clock Path between two flip-flops

Data Path refers to the path that data takes from the output of the launch flip-flop (or source register) to the input of the capture flip-flop (or destination register). The data travels through a series of logic gates and interconnects before reaching its destination.

Clock Path is the route that the clock signal takes to reach the launch and capture flip-flops. The clock signals trigger the launching of data from the source flip-flop (register) and capture it at the destination flip-flop (register).

Analogy for Better Understanding

Think of the data path as a car travelling on a road, while the clock path is like a set of traffic lights controlling the flow of cars. The traffic light at the launch flip-flop tells the car when it can start its journey, while the traffic light at the capture flip-flop tells it when it must stop. The goal is for the car (data) to reach the next traffic light (capture flip-flop) before it turns red (capture clock edge).

If the car reaches too late (negative slack), it violates the timing, much like running a red light.
If the car arrives just in time (zero slack), it barely makes it.
If the car arrives with extra time to spare (positive slack), it has a comfortable margin.

That brings us to the end of the SLACK discussion. Have you still survived? Excellent, let’s move on then!

2. SKEW

SKEW can be defined in many ways, yet all the definitions have the same gist:

The difference between the clock arrival time across the chip.
The time difference between a clock signal’s actual and expected arrival time.
The timing differences between signals in a clock distribution system.
The variation of the arrival of the clock at destination points in the clock network.
The temporal difference between the arrival of the same edge of a clock signal at the clock pin of the capture and launch flops.
The difference between capture and launch flop delay.

The root of the existence of Skew lies in the fact that signals take time to move from one location to another. Clock Latency is the time a clock signal takes to move from the clock source to the clock pin of a particular flip-flop.

For example, assume the capture clock delay is 2.5ns while the launch clock delay is 0ns. The difference between them is 2.5ns — 0ns = 2.5ns, which is the clock skew value.

Ideally, the clock should simultaneously reach the clock pin of all the flip-flops in a design, resulting in Zero Skew. However, this is not attainable owing to varying wire-interconnect lengths and temperature changes.

Also, the flip-flops placed near the clock source on the chip will get the clock early compared to the ones placed far away.

Local Skew and Global Skew:

Local Skew is the difference in latency between two related flops in a design.

Global Skew is the difference in clock delay between two unrelated flops or the difference between the longest and shortest clock paths in the design.

Positive and Negative Skew:

Positive Clock Skew occurs when the capture clock comes later than the launch clock. So first, the launch flop will get the clock, and then the capture flop. In this case, the capture clock delay is greater than the launch clock delay. Positive Skew is advantageous for setup timing. Due to the inclusion of skew, the capture clock is delayed by a few nanoseconds. Therefore, the timing path requires one clock period and skew margin to match the setup requirement.

Negative Clock Skew occurs when the capture clock comes earlier than the launch clock. So first, the capture flop will get the clock, and then the launch flop. It is beneficial for hold time since it delays the fresh launch. The prior data will be effectively recorded and will not be overwritten because of the delay in launching the new data. However, a negative skew is detrimental to setup timing.

Useful Skew:

Useful Skew is the skew that is purposefully/intentionally introduced into the design to satisfy timing and resolve violations. It is mainly introduced in clock pathways where timing fails so that timing is passed in that path. However, useful skew cannot be applied arbitrarily. This must be done with caution, ensuring that the margin is accessible in both the preceding and subsequent time paths. Uncontrolled skew insertion might result in further timing violations rather than resolving them. Useful Skew may be used to correct both setup and hold errors.

Harmful Skew:

While introducing some skew to the failed pathways might aid in resolving timing violations, too much distortion can result in violations. The capture clock will arrive late if a large positive skew is introduced into the design. If the data path delay between the two flops is small, the data may reach the D pin of the capture flop even before the capture edge reaches the clock pin of the capture flop. This overwrites the previously latched data, resulting in a hold violation. If a significant negative slack is included in the design, the clock edge will arrive at the capture flop before the launch flop. Hence, too much skew can cause violations that lead to Harmful Skew.

How to Mitigate Skew?

Mitigating Skew is essential for enhancing synchronization, robustness, jitter control, noise reduction, and overall circuit reliability. The primary goal is to minimize or eliminate both positive and negative skew, ensuring that clock signals reach different parts of the circuit at the right time.

Key techniques include:

Clock Tree Synthesis (CTS) involves balancing wire length, capacitance, resistance, and buffering within the clock network to ensure that clock signals arrive simultaneously at different flip-flops. It uses delay elements or phase shifters to equalize clock arrival times and reduce skew.
Clock Gating selectively turns the clock signal on or off in specific parts of the circuit based on their activity or logic state. This not only reduces power consumption but also minimizes noise within the clock network.
Adaptive Clocking dynamically adjusts the clock signal’s frequency or phase based on real-time feedback from the circuit or environmental factors. This technique compensates for variations in fabrication, temperature, voltage, and load conditions, thereby improving the circuit’s performance and reliability. By continuously tuning the clock signal, adaptive clocking helps maintain balanced timing and reduce skew.

So that was all about SKEW! Are you still reading? Wow, you truly are a VLSI aficionado!

Let’s move to the last topic of this blog, SLEW.

3. SLEW

Again, here are a few different flavours of definitions:

SLEW is defined as…

The time it takes for a signal to transition from one voltage level to another.
The rate at which a signal (its voltage) transitions from one logic level to another or simply the rate of change of voltage with respect to time.
The slew (slew rate) is also known as transition delay.

It is typically measured as the time it takes for a signal to rise (rise time) from 10% (or 20%) of its maximum voltage value to 90% (or 80%) of its maximum voltage value OR to fall (fall time) from 90% (or 80%) of its maximum voltage value to 10% (or 20%) of its maximum voltage value.

Slew, a.k.a Slew Rate, is typically measured in Volts per nanosecond (V/ns) or Volts per microsecond (V/µs) or similar units, depending on the speed of the transition.

Slew affects power dissipation, latency, and pulse width.

Propagation Delay:

Propagation Delay is the time required for a signal to propagate through a cell, gate or interconnect (net). If it is a Cell, we can call it Cell Delay; if it is a Gate, then Gate Delay; or if it is an Interconnect (Net), then we can call it Interconnect (Net) Delay.

The propagation delay of a gate or cell is the time it takes for a change in the input signal at the input pin to produce a change in the output signal at the output pin.

Generally, for any gate, propagation delay is measured between 50% of input transition and the corresponding 50% of output transition.

There are four possibilities:

Propagation delay between 50% of input rising (↑) to 50% of output rising (↑).
Propagation delay between 50% of input rising (↑) to 50% of output falling (↓).
Propagation delay between 50% of input falling (↓) to 50% of output rising (↑).
Propagation delay between 50% of input falling (↓) to 50% of output falling (↓).

Each of these delays has different values. The maximum and minimum values of these sets are very important. Maximum and minimum propagation delay values are considered for timing analysis.

Interconnect Delay is the delay between the time a signal is first applied to the interconnect/wire (net) and the time it reaches other devices connected to that interconnect/wire (net).

Propagation delay is taken as the average of rise time and fall time.

Propagation delay depends on the input transition time (slew rate) and the output load/capacitance. Hence, two-dimensional look-up tables are used to calculate these delays which are present in the Liberty Timing Library (.lib) file.

Impact of Slew on Circuit Performance:

Signal Integrity: A slow slew rate can lead to signal integrity issues such as glitches and noise, potentially causing incorrect data interpretation.
Timing: High slew rates can reduce the signal transition time, leading to faster circuit operation. However, extremely fast slew rates can cause timing violations like hold time failures.
Power Consumption: A faster slew rate generally means higher switching activity, leading to increased dynamic power consumption. Conversely, slower slew rates can increase leakage power.
Electromagnetic Interference (EMI): A very high slew rate can increase EMI, leading to crosstalk between adjacent wires and affecting signal integrity.

Factors Affecting Slew Rate:

Driver Strength: The strength of the driving cell (e.g., an inverter or buffer) influences the slew rate. Stronger drivers typically produce faster slew rates.
Load Capacitance: The capacitance seen by the driving cell affects the slew rate. Higher load capacitance results in a slower slew rate as more charge needs to be transferred to change the voltage.
Wire Resistance and Capacitance (RC): The RC characteristics of the interconnects (wire resistance and capacitance) also impact the slew rate. Long wires with high resistance and capacitance can slow down the signal transition.

Slew Rate in Timing Analysis:

Setup and Hold Time: Slew rate impacts setup and hold time margins. A slower slew rate can increase the uncertainty in setup and hold time calculations, leading to tighter timing constraints.
Propagation Delay: The delay of a signal through a gate or interconnect is affected by the input slew rate. This is captured in timing analysis through delay tables that consider input slew and output load.
Noise Analysis: Slew rate is critical in noise analysis as it impacts the peak noise voltage and the duration of noise pulses, which can affect circuit stability.

Controlling Slew Rate:

Buffer Insertion: Adding buffers or repeaters can help manage the slew rate, especially in long interconnects, by boosting the driving strength and reducing load capacitance.
Cell Sizing: Selecting appropriate cell sizes during synthesis or optimisation can control the slew rate. Larger cells with higher drive strength result in faster slew rates.
Wire Sizing and Spacing: Adjusting the width and spacing of interconnects can optimise the RC characteristics, thereby controlling the slew rate.

That’s about it, peeps! I hope that through this blog, you learned something new and interesting and that all the confusion regarding the three musketeers — Slack, Skew, and Slew — has been removed.

If you liked the memes and the blog’s content, then applaud, respond, and share this useful learning resource with your VLSI buddies.

Thank you for reading! Dhruvkumar Vyas, signing off! ✌️

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