History of Bitcoin Mining Hardware

  1. Pre-calculation: Remove as much as logic as possible from the hashing loop (C+5%, E+5%).
  2. Toggle rate reduction: Reduce average gate toggle rate (E+1%).
  3. Dynamic frequency control: Let every hash core operate on it’s best frequency (P+20%).
  4. Hand place and route: Makes space for more hash cores in the FPGA (P+15%). FPGA toolchain limitations made this a very hard effort.
  5. Over Voltage: The power distribution system of FPGAs is not designed for high power operation, so it drops a lot of voltage. Even when you power 1.2V at the PCB, on silicon you will have less than 1.0V due to package drop, which is a big performance hit. We couldn’t change the chip design (yet), so the only way to counter this was to supply the chip with higher voltage (P+30%).
  6. Miner management bus and protocol: Design for managing large amounts of miners, using minimum wire count. That saved cost for large scale operation (C+5%), and continued into the ASIC era.

Efficiency ∝ TCV²
(T=toggle rate, C=capacitance, V²=voltage squared)

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