Memory — SRAM cell
SRAM — Static Random Access Memory. What do the terms mean? Let’s break it down. Static implies that the memory will retain its stored value as long as the power supply is on. When the power is off, all bets are off, thus the Random Access Memory (RAM). To store values when the power is off, we need what is known as non-volatile memory. The alternative to SRAM is a DRAM or Dynamic Random Access Memory, which forgets the value stored in it even if the power is on if unattended for a while. DRAMs have to be periodically refreshed, which is one of the functions of the DRAM controller. SRAMs are generally used for lower levels of cache, typically L1 and L2 cache. The basic architecture of the memory is arrays, defined by rows known as word lines, which come out of a row decoder fed some number of bits of the address, and columns known as bit lines. Some number of bit lines are combined to read out by the column multiplexer and the bottom of the columns have the read and write circuitry. Each place where the column crosses the rows, there is a memory cell.
A 1024 x 32 memory implies that ten bits of input address are decoded into 1024 (2¹⁰) rows and 32 bits of output are read out. What do the memory cells look like? The most fundamental cell is the 6T (6 transistors) SRAM cell. The density of the cells is paramount, as increase in density of one cell implies an increase in all cells and thus the entire memory, which is already huge to begin with. There are various other types SRAM cells, such as 8T and 10T SRAM cells. In the memory, the columns carry not only bit but a complement of bit, which are attached to the cell on either side. The cell itself consists of two cross-coupled inverters along with two nFET devices known as access transistors, which are connected to wordline. The cell is completely symmetrical.
How does the cell work? Before both reading or writing, bit and bit bar lines are precharged i.e. pulled up to the supply voltage voltage, to have a value of logic 1. While reading, a wordline is selected (turned on) by the row decoder, by which the access transistors are switched on. The row-decoder produces a one-hot output based on the input address bits, which turns on only one row. During a read operation, depending on the state stored on the cross-coupled inverter, one of which will store a zero and the other a one, either the bit or bit-bar line is pulled down to ground, which is detected in the read circuitry to indicate what is stored. During a write operation, a word lineis selected which turns on the access transistors, and along with this, either bit or bit bar is actively pulled to ground. This flips the value of the cell if the cell had the opposite value, or retains the value if the same value was stored in the cell.
Read Stability
When wordline is turned high, it is possible that the precharged bit and bit bar lines can upset the value in the SRAM cell, and make it unstable. Let the nFET of the inverter be on, and the output node on the inverter be 0. When worldline is high and the access transistor is on, the precharged bit bar line must not overpower the nFET pulling the node to ground and flip the cell’s value. Weakening the access transistor relative to the inverter’s nFET ensures read stability.
Writeability
During the write phase, the access transistors are on, and one of the inverters is actively trying to hold the node to high while we want to flip this node to ground to write the cell. The bit or bit barline is actively driven to ground with an nFET or a pair of nFETs through the access transistors. Let the bit bar line be pulled to ground in this scenario. The nFET trying to pull the bit bar line to ground is fighting the pFET of the inverter to do so. To write the cell, the pull-down circuitry must be stronger than the pFET trying to keep the node high to ensure the cell is written. The pull-down circuitry consists of the write circuitry, the access transistor and the pFET, which drives the relative sizing of the transistors. Writeability is ensured by making the pFET of the inverter weaker relative to the access transistor.
Butterfly Diagram of a cross-coupled inverter
Let’s sidetrack from memory for a bit to talk about the butterfly diagram. The Voltage Transfer characteristic (VTC) of the circuit is how the output voltage changes with respect to the input voltage. Plotting the VTC of the two cross-coupled inverters in the memory cell on the same axis, we get the diagram in Figure 5.
The two curves of the inverters intersect at three points, thus the inverters have three possible operating points. The two operating points on the X and Y axis are the stable operating points that hold one of the two logic values: one inverter holds a 1 and the other a 0. The third operating point, when the curves intersect in the middle of the axis, is unstable and referred to as the metastable state. When the inverters are in a metastable state, they will eventually fall off the state and settle into one of the two stable operating points. How long this takes is indeterminate.
Let’s look at read stability and writeability through the lens of the butterfly diagram of the cross-coupled inverters. When the access devices are off, the butterfly diagram looks like the one in Figure 5. During the read phase, the pull-down nFET of one of the inverters is fighting either bit or bit bar. This leads the butterfly diagram to shrink. The size of the wings of the butterfly determines the noise margins of the SRAM cell which is defined as the largest square that can fit in these wings. If the wings get squeezed enough, the SRAM cell runs the risk of its value being upset.
During the write phase, one of the lines is actively high and the other is pulled low. When the access devices are turned on. one of the VTC curves will be the exact same as before, while the the pull-up of the other inverter is severely challenged due to the node being pulled to ground, and the inverter not being able to fight the bit or bit barline being pulled to ground can only pull-up the node to a lower value than VDD. The two curves only intersect at one point now, there is only one operating point which is the written state of the cell since the butterfly diagram has been pulled apart, and signifies that the cell is written.
If the butterfly diagram doesn’t open up fully and still has two stable operating points, the cell is not writeable anymore.
That’s all for now! In the next one, we shall look at the peripheral circuits of the SRAM for read, write and decode. I hope this story provides you with value and helps you dive deeper in the field of electronics and chip design. Thank you and have a good day :”)