Of Computer Memory | Part 1

RGB Ram!


At my current internship I am have chosen to get into devops. The term can be controversial in different spaces and a SysAdmin or Google’s SRE maybe more appropriate.

The saying Give me six hours to chop down a tree and I will spend the first four sharpening the axe ~Abraham Lincoln

The saying comes to mind although the realities may not be so as day to day problems arise and some need a quick fix but also a retrospect on the past is in order. Therefore I will be rolling out a blog post approx. every week which will be a deep dive on the major internals of the computer, this week being RAM. This week will be dominated with theoretical parts.

Off to the Races

In most of the computer’s internals there exists a hierarchy. This is as a result of the mismatch of memory being slower than the system’s bus. Some history of early computers and their storage is here. I wont go into details of the memory cell but the information can be obtained from here.

Hierarchy of Computer Memory

Disk storage(ssd, sshd or hdd) can be used in place of main memory but would choke the CPU as it’s much more faster than it. So there is that.

The reason for this hierarchy is mainly because of the three common trade-offs.

  1. Capacity
  2. Speed
  3. Cost

Trying to get a balance of the three is quite hard and outright disastrous and mainly you ought to be going for two of the three. Going down the hierarchy:

  1. Decreases the cost per byte.
  2. Increases the capacity.
  3. Increases the access time.

It is due to this that you can have a cost of say 8GB of Random Access Memory being equivalent to something like 1000GB of a hard disk drive an approx. 100 fold reduction of storage capacity but a 333,333% increase on speed.

The main reason that this works in all the three characteristics above is because of the reduction in frequency of access of the memory by the processor. Due to the nature of programming, instructions and data tend to cluster in loops and subroutines. In so, in the short term things will remain relatively the same but in the long term things are bound to change.

From this emerges to properties of memory references:

  1. Temporal locality — if a location is referenced, it is likely to be referenced again in the near future.
  2. Spatial locality — if a location is referenced it is also likely that locations near it will also be referenced in the near future.

It’s therefore important to have a balance in capacity and speed as a system’s performance is dependent on it e.g If the main memory was much smaller than expected in a production environment and you have evidence that some processes have a lot of delays and your usage of the main memory is constantly above say 85%, it may be bad architecture/choice of programming language on your side but also it may be tell of your unbalance of the main memory capacity.

Memory Locations WRT to the CPU & Processor

  • Inside the CPU — registers
  • Inside the Processor — L1 cache
  • Motherboard — Main memory and L2 cache
  • Main Memory — DRAM and L3 cache
  • External — disk storage, network memory devices, tapes etc

Important Units in Memory

The natural data size for a processor is a word. A 64 bit processor has a double-word = 64 bit word.

Some useful conversions and terms …

  • bit A single binary digit, that can have either value 0 or 1.
  • byte 8 bits
  • nybble 4 bits
  • word 32 bits
  • halfword 16 bits
  • double-word 64 bits
  • Kilobyte 1024 bytes
  • Megabyte 1024 Kilobytes
  • Gigabyte 1024 Megabytes
  • Terabyte 1024 Gigabytes
  • Petabyte 1024 Terabytes etc. ….

This is important as it is defined by the data bus width i.e a 32-bit computer can only be able to carry 32 bits worth of code and data while a 64-bit computer is capable of double that.

About Caches ….

The caches are important in this hierarchy as it is a mid-point in both costs and access time. They exploit the two properties of memory reference.

In cache operations, the CPU requests the contents of a memory location(s). The cache has to check for this data and if present(cache hit) get it, else(cache miss) it must read from a level down from its position a block e.g from main memory to the L3 cache. The tags are important in distinguishing which blocks of main memory are in each slot.

What Causes a Cache Miss

It is important to note some causes of a cache miss.

  • Compulsory misses — first access of a memory block
  • Capacity misses — cache cannot contain all blocks needed by the system and its applications.
  • Conflict misses — caused by a block that has been replaced by another block and which is later retrieved


This is was a short blog post and in the next issue I hope to cover more about the Main memory structure(page tables), the operations involved by the kernel, the heap and stack.


https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Data/bitBytes.html https://en.wikipedia.org/wiki/Memory_cell_(binary) https://en.wikipedia.org/wiki/Random-access_memory https://en.wikipedia.org/wiki/Memory_hierarchy