AgnathavasiSimple English storieshttps://www.scribd.com/document/14650241/Japanese-Fairy-Tale-Series-01-12-The-Cub-s-TriumphMar 13Mar 13
AgnathavasiSome Physical Design QABelow is the Timing team interview questions: 1)Explain about your work done in past 2) How you finalize floorplan 3) How you solve timing…Mar 122Mar 122
AgnathavasiHow are insertion delay and timing interrelated in VLSI PD?In VLSI (Very Large Scale Integration) physical design (PD), insertion delay refers to the additional time taken for signals to propagate…Feb 151Feb 151
AgnathavasiWhy do we consider CPPR in SI timing analysis?CPPR is the common path pessimism reduction and needs to be considered wherever appropriate to remove the unwanted pessimism you are adding…Feb 15Feb 15
AgnathavasiGoals of CTSThe primary goals for clock tree synthesis are minimum or zero skew, minimum latency and acceptable clock tree power. I’ll explain the…Feb 11Feb 11
AgnathavasiPlacement Stage , How do you fix Setup/Hold Voilations during the placement stages?At placement stage, one should only focus on fixing setup violations as the clock tree is still not built at that phase in the design flow.Feb 11Feb 11