CMOS FABRICATION (P-WELL PROCESS)

CMOS means Complementary Metal Oxide Semiconductor. It is used to fabricate digital circuits and IC chips. It is a combination of NMOS (N-type Metal Oxide Semiconductor) and PMOS (P-type Metal Oxide Semiconductor) transistor pairs that are symmetrical. CMOS fabrication can be carried out in many ways. P-well is one of the processes in which CMOS circuits are realized.

Making of CMOS using P well Technology

The CMOS fabrication steps of the p-well process are the same as that of an n-well process except that instead of an n-well a p-well is implanted. the process starts with an n-type substrate.

Step 1: A thin Sio2 layer is deposited on an n-type semiconductor material which acts insulator to the environment.

Step 2: Using chemical vapor deposition (CVD) the thick silicon nitride(si3No4) layer is deposited on the SIO2 layer.

Step 3: A plasma etching process is used to make trenches for insulating the device from the external environment.

Step 4: These trenches are filled with Sio2 which is called the field oxide which insulates the device.

Step 5: Using the mechanical planarization process the sacrificial nitride layer and the pad oxide are removed until the flat surface is on the layer.

Step 6: To adjust the doping process the p-well areas are exposed with masks and later annealing and implant are applied. This is followed by a second implant step to adjust the threshold voltage of the NMOS transistor.

Step 7: The implant step is performed to adjust the threshold voltage of the PMOS transistor.

Step 8: The metal contacts are made at the positions and the grounds are connected which prevents the device from high currents and voltages.

Step 9: Ion implantation is carried out at the source and drain regions of PMOS (p+) and NMOS (n+) transistors, this will also form the n+ polysilicon gate and p+ polysilicon gate for NMOS and PMOS transistors respectively. This process is also known as the self-aligned method.

Step 10: Oxide and Nitride spacers are formed by the chemical vapor deposition.

Step 11: Holes are etched, metal is deposited, and patterned. After the deposition of the last metal layer final over-glass is deposited for protection.

Significance of P well

• Consumes low power: P-well CMOS transistors consume low power and operate efficiently.
• Less sensitive: P-well CMOS devices are low sensitive that is they can withstand high currents and voltages
• Source to body not possible: Unlike n-well, the source to the body is not possible in p-well devices.
• Flexibility in manufacturing: P-well is mostly used CMOS type due to its flexibility in manufacturing.

***********************************************

Why do we use p substrate in CMOS?

Starting with a p-type substrate allows one to build n-channel transistors without additional doping. That is the main advantage of the P substrate.

Reason for used P-substrate in CMOS

NMOS is faster than PMOS, because the carriers in NMOS, which are electrons, travel twice as fast as holes, which are the carriers in PMOS. Now P substrate has the majority carrier is holes, now if we are using an n-substrate, we need to form a p-well inside to form NMOS, now as we have hole mobility, less than electrons, now we need to form a p-well by counter doping, so with that again we are decreasing hole mobility, so it may degrade the performance of NMOS, so we are using p substrate in CMOS.

The second reason is that if we create a P-well above the N-type substrate, to get maximum electron mobility in NMOS we need a very high resistive (high doping) P-well, which is a costly process. So, the fastest NMOS was obtained with a high resistive P substrate, not a lower P-well in an N-type substrate.

The third reason is in a p-well technology, such a choice would degrade the gain due to the body effect of pMOS transistors (coming as a second cause for gain degradation after the “low mobility of holes” cause).

The fourth reason is, The p-type doping of an original silicon wafer is more uniform than any doping that can be obtained by introducing a p-well into a silicon wafer. The only methods to create a p-well are by diffusion or ion implantation and both have inherent non-uniformity with depth into the substrate.

Fifth reason is p-type substrate allows one to build n-channel transistors without additional doping. This is a substantial advantage because, the lower the doping, the higher the mobility of electrons and the higher the gain, and the higher the switching speed of transistors.

The sixth reason is the p substrate is less suspect to noise as compared to the n substrate.

The seventh reason is if We use n substrate then the whole plate needs to be tied with power(VDD), which may create leakage.

What is a p-type semiconductor?

An inherent semiconductor doped with boron (B) or indium is known as a p-type semiconductor (In). Boron from Group III has three valence electrons, while silicon from Group IV has four.