IC LAYOUT

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. Originally the overall process was called tape-out as historically early ICs used graphical black crepe tape on mylar media for photo imaging

When using a standard process where the interaction of the many chemicals, thermal, and photographic variables is known and carefully controlled — the behaviour of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes.

If there’s just one aspect that distinguishes the backend design from frontend design, then it would be- delay. Frontend design, while being cognizant of the logic delays and speed, largely ignores it for the majority part of the RTL coding and verification. While, on the other hand, the physical design sees real delay right from the very beginning.

Using a computer-aided layout tool, the layout engineer or layout technician places and connects all of the components that make up the chip such that they meet certain criteria — typically: performance, size, density, and manufacturability. This practice is often subdivided between two primary layout disciplines: Analog and digital.

The generated layout must pass a series of checks in a process known as physical verification. The most common checks in this verification process are

• design rule checking (DRC),
• layout versus schematic (LVS),
• parasitic extraction,
• antenna rule checking, and
• electrical rule checking (ERC).

In the earlier, simpler, days of IC design, the layout was done by hand using opaque tapes and films, an evolution derived from early days of printed circuit board (PCB) design — tape-out.

Modern IC layout is done with the aid of IC layout editor software, mostly automatically using EDA tools, including place and route tools or schematic-driven layout tools. Typically this involves a library of standard cells. The manual operation of choosing and positioning the geometric shapes is informally known as “polygon pushing”.

The IC Layout Engineer is responsible for converting an electrical design to a mask layout used for chip fabrication. He is responsible for the physical representation of the chip, from the lowest block level to the complete floor plan. This will be done in close collaboration with the circuit designers and project leaders.

IC layout flow is further sub-divided into the following:

1. SYNTHESIS

Synthesis reads in the RTL code (.v or .sv files) along with physical libraries of the standard cells that may contain delay information (.lib files), physical dimensions and metal layer information within the cell (.lef files) and other constraint files to convert the behavioural or dataflow code into real physical standard cell gates.

2. FLOORPLANNING

Floorplanning step formalizes and refines the floorplan that was first conjured up during the architecture planning step. In this step, the entire die area is divided into physical partitions, and their shapes are moulded while keeping in mind the area requirements, the flow of top-level data and control buses, the possibility of any future growth. Pins and ports are assigned a rough location, which can further be refined depending on the Place and Route results.

3. PLACEMENT

During placement, all standard cells are placed in legal locations on-site rows. This step aims to minimize the wire length while ensuring optimal placement that will help faster timing convergence.

4. CLOCK TREE SYNTHESIS

During clock tree synthesis, clocks are propagated and the clock tree is synthesized using clock buffers. The major goals of this step are to achieve optimal clock latency while minimizing clock skew. There are many proposed algorithms to design an optimal clock tree- H Tree, Steiner Tree etc.

5. DETAIL ROUTING

With all instances placed and clocks routed, now it’s time to route the signal nets. The modern process supports 10–12 metal layer stack, with M0-M1 reserved for standard cell routing. The algorithm used for detail routing is usually a glorified maze router with added constraints to ensure faster run-times. The metal resources are divided into tracks which are the legal locations for metal routes. Aim of detail routing is to ensure minimum detours because these may have implications on timing, and to ensure minimum DRC (Design Rule Check) violations like opens, shorts etc. This step performs multiple search and repair loops (10–20) to keep the overall DRC count low.

6. PHYSICAL AND TIMING VERIFICATION

While logic verification ensures correct functionality, physical verification ensures the correct layout. There’s been an increase in Physical Verification checks which includes- DRC (Design Rule Checks), LVS (Layout versus Schematic), Electromigration, Electro-static discharge violations (ESD), Antenna violations, Pattern Match (PM) violations, Shorts, Opens, Floating nets etc. It is important to track these violations in parallel with the Place and Route flow to avoid any surprises just days before tape-out.

Timing Verification verifies that the chip runs at the specified frequency by ensuring setup and hold is met for all timing paths in the design.

SOME MODELS OF IC LAYOUT