1st-CLaaS — An Open Source FPGA framework
Have you ever wondered how to make customized hardware designs? Gone are the days when only big commercial giants had the tools/accessories to establish proprietary designs and fabricate them. Due to the rise of open-source tools, that provide a similar workflow for FPGAs, ASICs as well as the Simulation of designs, it's just a matter of creativity and good programming skills in HDL to establish your customized hardware design fully simulated and tested on actual hardware. To test the design on hardware, the user may require an expensive FPGA board and commercial EDA tool to generate the bitstream of the design for deployment. Another possible way is to use a Cloud-based FPGA hardware service to test and deploy your design which is less expensive (for testing your design, about 2 dollars an hour) but consists of quite a hassle to establish the setup. That's where 1st-CLaaS steps in to provide a complete user-friendly workflow in deploying your design on actual Cloud based FPGA hardware to understand better and test your design before moving forward with ASIC.
1st-CLaaS, A Journey
1st- CLaaS, an acronym of 1st- Custom Logic as a Service is an open-source framework that provides the user an ease to develop, test, and deploy his designs. My journey with 1st-CLaaS started back when I learned TL-Verilog (It's a Hardware Descriptive Language which is explained in the next section) in MYTH (Microprocessors for You in THree weeks) Workshop. Being a Verilog programmer for quite some time, learning TL-Verilog seemed a little odd at first but later I realized how useful it would be in complex designs to test and visualize them using Viz (Visualization of design as easy to understand schematic). Here is a short demo of the RISCV core I designed in TL- Verilog during the MYTH workshop.
How to write your designs?
The conceptual design of the hardware is written using a hardware descriptive language (HDL) and is known as Hardware Kernel
You might have heard of Verilog/SystemVerilog, which are the traditional HDLs used for years to write hardware designs. They get the job done but have a steep learning curve and it is sometimes a headache to code up complex pipelined designs that may require rework from time to time (i.e. to match the setup time of the designs). TL-Verilog, an alternative yet a user-friendly HDL that doesn’t have a steep learning curve comes to the rescue. Users can develop designs easily without getting into the complexity of even writing test benches to test the design. The design is compiled with SandPiper SaaS, which converts it to Verilog so that Open-source tools like Verilator can simulate the code. I have attached some TL-Verilog learning materials in the references as well.
The good thing is, that 1st- CLaaS provides the workflow for the TL-Verilog-based designs to be compiled and simulated. Moreover, an online platform known as Makerchip is established as well to avoid the hassle of downloading tools and establishing setups and the user can simulate the design just from his browser.
GSoC and My Contribution
Contributing to open source and want to earn some bucks as well? GSoc known as Google Summer of Code provides the opportunity to students and professionals to contribute to open source projects and get stipends as a reward. GSoC gave me an opportunity to contribute to 1st-CLaaS and I learned a lot in this journey. Following are some of the key intakes during the summertime:
Updating AWS Machine Image: 1st-CLaaS is based on Cloud FPGA infrastructure and AWS is its backbone. 1st-CLaaS was developed back in 2019 but within the 4-year timeframe, the infrastructure of 1st-CLaaS became unstable. The user was limited to only simulating the design but couldn’t establish a remote instance. In 1st-CLaaS, the AWS configurations are automated using Terraform which has a learning curve but is worth it. I was able to stabilize the AWS instance creation flow back to live.
Rework for Vitis: AWS instances have Xilinx Tools being setup by default because their Cloud FPGAs are Xilinx-based. After 2020, Xilinx upgraded/updated their tools, deprecated SDAccel (for software acceleration), and introduced a unified Vitis flow. Due to these changes, the 1st-CLaaS automated setup based on Makefiles, Bash, and Tcl scripts got disrupted. During the project time, rework was being done to refurbish the scripts with new commands and correct any bugs along the way.
Reviving Hardware Emulation: 1st-CLaaS supports three modes to test out your design. Simulation (2-state), Emulation (HW), and FPGA Hardware Deployment. The Emulation mode was established on a software development kit (SDK) and a deprecated tool SDAccel. In Hardware Emulation (and Hardware mode), the hardware kernel has an interaction with a host application that is based on OpenCL. The design then gets hosted on a web server that transmits and receives data from the hardware kernel. This flow was damaged which was the main component of 1st-CLaaS. Reviving this flow was challenging but we (me and my mentor) were able to overcome the issues faced along the way such as updating the OpenCL calls, adding the correct emulation configuration file, sourcing the right and updated scripts, and updating the Makefile. We used different debugging techniques to achieve this milestone. One of the error messages we faced was the Segmentation fault (core dumped) and it was due to the hardware kernel not being initialized properly by the OpenCL call. The working flow looks like this:
Configuring Initial Setup for F4PGA: The beauty of 1st-CLaaS is it has vast opportunity to get expanded with further deployment options. One of the major goals of the project was to fully establish and test out the F4PGA integration with 1st-CLaaS. However, the hassle of stabilizing different components of 1st-CLaaS and the unavailability of on-premise FPGA hardware consumed the time and we were unable to establish and test out this functionality at its fullest.
Major Takeaways
1st-CLaaS provides a robust environment for the user to test out his custom kernel on actual hardware or emulate it. The time-consuming process of deploying the design using the AWS platform is automated at its fullest so that the user can focus on writing out the hardware kernel and not worry much about spending time on deployment.
Contribution Links
Github Pull Request For Stabalizing 1st-CLaaS: https://github.com/os-fpga/1st-CLaaS/pull/80
Github Pull Request for Initial changes for F4PGA: https://github.com/os-fpga/1st-CLaaS/pull/82
Credits
The credits and efforts for mentoring the project work on 1st-CLaaS goes to Steve Hoover, CEO of Redwood EDA. His constant guidance and commitment helped to achieve our desired goal.
Future Work
Testing out F4PGA on local FPGA and completely automating the flow for students.
Upgrading the hardware kernel wrapper used for webserver.
Reworking the webpage setup for Mandelbrot to be more aesthetic
Introducing further applications as examples in 1st-CLaaS repository
References
[1] My RISCV core in MYTH : https://github.com/RISCV-MYTH-WORKSHOP/risc-v_myth_workshop_eeview_may2023-Shelby-dotcom/tree/master/Day3_5
[2] TL Verilog Learning resource: http://www.makerchip.com/sandbox/#
[3] F4PGA Docs: https://f4pga-examples.readthedocs.io/en/latest/getting.html#getting