Annesha BaruahImpact of Clock Insertion Delay on different technology nodesThe amount of time taken by the clock signal to travel from source to the clock sink pin of the register is the clock insertion delay…Nov 9, 2019Nov 9, 2019
Annesha BaruahNDR AnalysisNon Default Rules are a set of rules that we apply on critical nets which cannot meet the timing requirement due to variety of factors…Nov 9, 2019Nov 9, 2019
Annesha BaruahDummy LEF generationLEF is the Library Exchange format of a design. It basically consists the physical definition of the block or chip. These include the…Nov 9, 2019Nov 9, 2019