The ability to perform real-time, low-latency and deterministic processing at the edge is increasingly important for a range of applications, from autonomous vehicles to vision guided robotics and intelligent surveillance systems.
Processing at the edge is required for four main reasons availability, latency, security and determinism. Should wireless communications be used to communicate to and from a cloud service where the processing is performed, connection to the cloud service cannot be guaranteed. As you might experience service outages and/or signal blackspots created by buildings or natural vegetation. …
Having looked at creating the virtual machine and the different build elements of PetaLinux.
In this blog I am going to demonstrate how we create a PetaLinux embedded Linux solution for our Zynq design. In this case we are going to use the Cora Z7 as the target development board.
To create an embedded Linux solution for our Zynq, Zynq MPSoC or MicroBlaze solutions we start with a hardware design in Vivado.
For this application we are going to connect the Zynq Processing System (PS) to the LED and Push Buttons which are on the Cora Z7. …
Having demonstrated how to get create a PetaLinux build environment, we are now in position to be able to start creating embedded Linux solutions.
As such in this blog we are going to look at the different elements which are included in a PetaLinux build and which might need configuration.
As always we will start with the highest level element and its configuration.
System — The main PetaLinux element which enables us to configure the highest level of our embedded Linux solution.
Elements which we may configure at the system level include, location of the RootFS e.g. INITRAMFS or External…
To get started creating a our PetaLinux solution we need to use a Linux Machine. In this blog we are going to look at how we can create a Linux Virtual Machine and Install PetaLinux. Once we have done this we are then able to create, build and experiment with PetaLinux projects.
To install PetaLinux our Linux machine needs at least the following
- 8 GB RAM
- 2 GHz CPU
- 100 GB free HDD
- OS — Red Hat Enterprise Workstation/Server 7.4 / 7.5 / 7.6 (64-bit)
- OS — CentOS Workstation/Server 7.4 / 7.5 / 7.6 (64-bit)
- OS — Ubuntu Linux Workstation/Server…
Over the years we have looked a lot at how we can use PetaLinux to create embedded Linux solutions for our Zynq, Zynq MPSoC and MicroBlaze solutions.
I thought it would be a good idea to dedicate a special series of blogs looking at PetaLinux, what it is and how we use it.
As such over this PetaLinux edition in addition to this introduction to PetaLinux, we are going to be looking at :-
- PetaLinux Build Environment — How to get started and what tools we need to create a complete PetaLinux deployment.
- PetaLinux Build Components — What are the…
In my last blog looking into Silexica’s SLX FPGA tool, I introduced the tool, its concepts and of course the benefits it brought in accelerating not only the performance but also development time. In this example, I continue to see big benefits of using the SLX FPGA tool when using Xilinx’s HLS flow. Specifically, I see a 42x improvement in latency from SLX FPGA while only seeing a 5x in area (LUTs).
In this blog we are going to look a little more in detail at the development flow, targeting industrial an application algorithm. Commonly these industrial algorithms are used…
Since the announcement of the Versal ACAP at XDF18, there has been great interest in the software environment which developers will use to leverage Versal ACAP and its vast capabilities.
Yesterday in the keynote at XDF19, it was announced the new unified software environment would be called Vitis and most exciting of all it would be available from the end of the month be heavily open source based and free.
Fortuitously, when I registered which sessions I wanted to attend at XDF, I had selected most of the unified software environment talks. …
Last week, we looked at how we could work with loops in our HLS source code, exploring how we can flatten, merge and unroll loops.
This week, we are going to look at how we can work with the HLS analysis perspective, so we can understand where our optimizations will have the best impact in our HLS source.
The analysis perspective is populated with information once we have run HLS synthesis and presents information regarding the hierarchy, resource utilization and most importantly latency of our design.
For our first example, let’s take a look at the loop merge example from…
When we write code intended for HLS implementations, we tend to implement repetitive algorithms that process blocks of data — for example, signal or image processing.
As such, our HLS source code in either C or C++ tends to include several loops or nested loops. When it comes to optimizing, performance loops are one on the places we can start exploring optimization.
By default, HLS loops are kept rolled. This means that each iteration of the loop uses the same hardware. Of course, this provides the worst performance as each iteration is sequential.
Let’s take a simple accumulator, as shown…
I have recently been evaluating the SLX FPGA tool from Silexica. If you are not familiar with SLX FPGA it is designed to work with both Vivado HLS and SDSoC.
SLX FPGA was created to help address the challenges software engineers face deploying C/C++ applications on to programmable logic targets using High Level Synthesis (HLS). These challenges include detecting parallelism within the design, and optimizing the design to be able to leverage the parallelism for increased performance.
This optimization is achieved by identifying and inserting appropriate pragmas to provide level of optimization desired.
To perform the optimizations, SLX FPGA analyses…
Adam Taylor
Adam Taylor is an expert in design and development of embedded systems and FPGA's for several end applications. He is the founder of Adiuvo Engineering Ltd
