Arpit GuptaRevisiting the RISC vs. CISC DebateRISC vs. CISC wars raged in the 1980s when the chip area and processor design complexity were the primary constraints and desktops and…Apr 8, 2019Apr 8, 2019
Arpit GuptaImproving Memory Scheduling via Processor-Side Load Criticality InformationMany microarchitectural techniques are being employed these days to remove/reduce stalls wherever possible. The paper by Dr. Saugata Ghose…Mar 26, 2019Mar 26, 2019
Arpit GuptaConcurrent Refresh Aware DRAM MemoryDRAM density has been alarmingly rising to meet the ever-increasing demand of the multi-programming and memory intensive applications…Mar 19, 2019Mar 19, 2019
Arpit GuptaTwo-way skewed-associative cachesThere is an inherent tradeoff between direct mapped caches and associative caches. Direct mapped caches improve the clock of caches since…Mar 4, 2019Mar 4, 2019
Arpit GuptaAdvanced Optimizations of Cache PerformanceIn this blog, I would review some of the optimizations to improve cache performance based on metrics like hit time, miss rate, miss…Feb 25, 2019Feb 25, 2019
Arpit GuptaAdaptive Insertion Policies for High-Performance CachingCaches act as a high-speed buffer between CPU and Main Memory. It improves performance by making the data needed in pipeline available…Feb 13, 2019Feb 13, 2019
Arpit GuptaValue Prediction in the Multi/Many-core EraResearchers, both in industry and academia, are trying hard to increase IPC in every possible way to improve the performance of the modern…Feb 5, 2019Feb 5, 2019