Reduce Risk with RISC-V Processor Design

Use formal verification with a tool you like to exhaustively prove that your design works

Formally verify your RISC-V designs in a scalable way with predictability

Designing RISC cores is easier, with the advent of open-source RISC-V ISA and a whole new eco-system being developed around software and tools. What is not discussed as much in the realms of RISC-V is the need and gaps in verification. Although, formal verification has received a lot more attention in the…