Altered Silicon: X16R mining on the Xilinx FPGA

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Virtex® UltraScale+™ FPGA

For a mining process that utilizes 16 different algorithms in random combinations roughly every few minutes, implementing acceleration of the X16R mining protocol using FPGA would be a huge challenge. But I needed it to work. I was very excited about a new blockchain project called Ravencoin and I wanted to use Ravencoin’s blockchain to essentially create a form of “supercomputing mining”, where a crypto called Ravencoin (RVN) would be output as result of compute services rendered. FPGAs and GPUs facilitate high performance computing services such as deep learning, genomics and financial data processing. GPU mining is already a known quantity. I would need FPGAs that could mine crypto and to achieve this, we would need to be able to teach this supercomputing hardware to mine.

I put it to my friend Arsen Julhakyan nearly 9 months ago over an espresso at a Union Square cafe in downtown San Francisco. Arsen had just arrived from the UK, where he had previously worked at ARM as a senior chip engineer. He hadn’t shown any signs of jet lag yet so I breathlessly explained what I wanted to do. He immediately dove into calculations. He loves to do this kind of stuff, like some kind of gladiator mathlete fighting algo-lions in the Nerdlympics. After considering max clock rate, power dissipation, algorithm size, efficiency losses, etc, etc, he seemed pretty confident that he could achieve it, but warned that when fitting compute cores and control logic into FPGA silicon, its anybody’s guess.

Flash forward some number of months. A lot of months would be more accurate. Arsen and his team have implemented, rolled, placed and routed 16 algorithms onto the latest high performance computing muscle: Xilinx’s Ultrascale+ FPGA processor. Fighting with timing errors, fitting approaches and reconfiguration schemes, we are finally mining our first RVNs using compute equipment that, for all intents and purposes, was never designed for this.

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Its come full circle for me — way back in 2012 I had used FPGAs to mine bitcoins. Using Xilinx Spartan FPGAs we achieved a ground breaking 1GH/s of hashrate using four Spartan FPGA chips operating in parallel. Nowadays the average bitcoin miner operates at about 13,500 times faster.

For a brief time, this was the best bitcoin miner on the market. Now, it would take about 165,000 years to make a bitcoin. Probably never.

That’s progress for ya.

FPGA for RVN is not a centralization threat
Often FPGA designs are the precursor to ASIC development, and the effort leads to a design that is permanently etched into silicon, creating a dedicated and powerfully efficient application-specific integrated circuit. Crypto mining ASIC chips have led to massive growth in the hashrate of some blockchain networks, but the tech has brought with it some centralization problems too — a concentration of mining power and coin wealth presents a threat to the security and safety of those blockchains.

One problem with developing mining ASICs is that highly efficient silicon is extremely expensive to produce. A manufacturer must have confidence that they can recover a huge investment within a relatively short period of time. During this time, new competitors could introduce better technology, or market conditions could change, eliminating profitability and market demand. ASIC chips are like little drag racing robots. They only know how to run really, really fast and are prone to crashing. And burning. And if the team that lines up next to you has a better engine? Well, you lose the race.

In the case of Ravencoin’s X16R algorithm, it just doesn’t make financial sense to try for it. The power efficiency improvement that can be achieved using even the latest 7nm process just doesn’t justify the risk that a) the chip might not work or may not be efficient enough and b) the market won’t change during the year-long development process or c) the X16R protocol gets changed, rendering the investment worthless. With ASIC development there are tens of millions, even hundreds of millions of dollars at stake. Who would risk it?

What about massive proliferation of FPGAs, won’t that create centralization of mining power?
Our FPGA bitstream produces 5 times more efficiency than an Nvidia 1080ti GPU. That’s pretty good — and it does this for only about 3–4 times the price. That represents a distinct advantage, but not a world-changing one. An ASIC would produce at least 50 times the hashrate for a manufacturing cost of $1. But the retail unit cost of a single FPGA card is as much as $4000. This is way too much for massive adoption to occur.

In addition, the economics of mining RVN are pretty challenging right now — FPGAs included. A single FPGA card would take 3 to 4 years to pay itself off. Those numbers are not likely to kick off a buying spree for this technology.

Lastly, Xilinx themselves are the manufacturer, and they wouldn’t make millions of chips the way the mining mining ASIC makers do. And they are not about to start. Even if demand were to skyrocket, Xilinx is well aware of the crypto-hangover currently being suffered by Nvidia (NVDA). By responding to the highly volatile mining market demand, Nvidia got stuck holding a giant bag. They are not likely to repeat this mistake, and their competitors have watched and learned.

So why did we make our FPGA miner?

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Data is Exploding

FPGA technology was developed to accelerate specialized computing tasks. Intensive data processing for applications in industries such as aerospace, bioinformatics, medical imaging, genomics, wired and wireless communication, finance, oil & gas and many more, shows that compute acceleration remains its best application, and Altered Silicon intends to remain focused on just that — offering world class data processing, but at a much lower price point. The data processing bitstreams we design are the cutting edge of a new form of supercomputing in the cloud — dense, powerful installations of machines running in low-cost cryptomining style facilities and subsidized by their ability to produce revenue 24 x 7.

I think the topic of tokenizing supercompute deserves its own article. So look for a Part Deux coming soon!



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