Dependencies in Chip Design Infrastructure
The first set of infrastructure which is defined on a chip design project is the interconnect, which consists of the module hierarchy, module ports, and connections between modules.
Each leaf leaf or intermedidate module can be tested with a test bench. The test bench components must mirror the module ports as shown in the diagram below.

Stimulus must drive both units. The design under test (DUT) can be modeled in an algorithmic or cycle accurate simulator. The input stimulus (either a test driver or the output of a previous unit(s) drives both the DUT and the simulation unit. The output of the simulation unit is captured either on clock cycle edges or at transaction boundaries. The output of the simulation unit is compared to the output of the DUT in a testbench.
The diagram shows the number of different components in the DUT, the simulator, the test, and the test bench which must be maintained. The depdency management of the components with the shared infrastructure specification creates endless cycles of updates driven by a change in one domain which must be replicated in other domains (parallel book keeping).
A more efficient way of generating and maintaining the infrastructure is to use a meta language/GUI to construct the meta description and then compile the meta description into the different file views/language files used by the different chip design teams.
