Big breakthrough for New ferroelectric transistors

Big breakthrough for Semiconductor chips! New ferroelectric transistors are smaller, faster, and more energy-efficient

Semiconductor chips are the core of modern information technology, and they can perform a large number of storage and computing tasks. However, with the explosive growth of big data, traditional silicon-based chips have been unable to meet the performance and energy consumption requirements. In order to break through this bottleneck, scientists have been looking for new transistor designs, one of the most promising ones is ferroelectric field-effect transistors (FE-FETs). FE-FETs use the polarization characteristics of ferroelectric materials to achieve non-volatile storage, and can also act as high-speed switches to perform logic operations. FE-FETs have the function of storage and computing integration, which can greatly improve data processing efficiency and reduce energy consumption.

Recently, Professor Deep Jariwala and his team from the School of Engineering and Applied Science at the University of Pennsylvania published a new paper in Nature Nanotechnology, introducing a new FE-FET design that has brought a great breakthrough to semiconductor chips. The design uses two-dimensional semiconductor molybdenum disulfide (MoS2) as the channel material and aluminum scandium nitride (AlScN) as the ferroelectric dielectric material, showing that these two materials can effectively combine to produce transistors with record-breaking performance. The design not only has the advantages of high efficiency, low power consumption, high speed and high density, but also has scalability and compatibility, which can be integrated with the existing complementary metal oxide semiconductor (CMOS) back-end line (BEOL) process to form a single-chip three-dimensional integrated circuit.

The key point of this design is that it can complete all the preparation processes at a temperature below 400°C, which meets the thermal budget of the CMOS BEOL process. This means that the design can be compatible with the existing chip manufacturing process without major modifications. In addition, the design can also minimize the polarization voltage and memory window (MW) by adjusting the thickness and scandium alloy concentration of AlScN. MW is the difference between the voltages required for programming and erasing, which reflects the reliability and stability of the memory. The team also demonstrated the application value of this design in computing, by achieving multi-bit storage (that is, one storage unit can store multiple bits of information).

In order to illustrate that this design has brought a great breakthrough to semiconductor chips, we can compare it with other types of transistors in terms of performance. According to the simulation results in literature, when the channel length is reduced to 15 nm, the unit gain cutoff frequency (fT) and maximum oscillation frequency (fmax) of this design reach 1.15 THz and 1.22 THz respectively, which are 15.4% and 22.5% higher than those of traditional InGaAs MOSFETs respectively. In addition, this design also has higher energy efficiency. When the channel length is 15 nm, its transconductance generation factor (TGF) and transconductance frequency product (TFP) reach 0.77 S/W and 0.85 THz/W respectively, which are 53.4% and 69.3% higher than those of traditional InGaAs MOSFETs respectively. These indicators show the superiority of this design in storage and computing.

The researchers who participated in this study also evaluated and prospected this design. Professor Jariwala said: “Because we use ferroelectric insulating materials and two-dimensional semiconductors to make these devices, they are very energy-efficient. You can use them for computing and storage-they can be interchangeable and efficient.” He also said: “The combination of MoS2 and AlScN is a real breakthrough in transistor technology. Other research teams’ FE-FETs have been plagued by ferroelectric performance loss caused by device size reduction, while our design can maintain ferroelectric performance at the scale required by industrial manufacturing.” He predicted that this design will provide a powerful candidate solution for achieving high-performance, low-power consumption, high-density and high-reliability storage and computing devices in the future.

In addition to Professor Jariwala, other researchers involved in this study also gave high praise to this design. Professor Olsson said: “Our work demonstrates a novel approach that can use ferroelectric materials to achieve integration of non-volatile memory and logic circuits at low temperatures. This integration can significantly improve data processing speed and reduce power consumption.” Doctoral student Kim said: “We successfully combined two-dimensional semiconductor MoS2 with ferroelectric material AlScN to produce FE-FETs with excellent performance. These FE-FETs can be prepared at temperatures below 400°C, meeting the requirements of CMOS BEOL process.” Professor Stach said: “We used advanced electron microscopy techniques to observe the interface between MoS2 and AlScN, and found that there were no defects or impurities between them. This shows the good compatibility between these two materials, which provides a solid foundation for achieving high-performance FE-FETs.”

References:

1: Kim, K.-H., Olsson, R. H., Stach, E. A. & Jariwala, D. Scalable CMOS-BEOL compatible AlScN/2D channel FE-FETs. Nat. Nanotechnol. (2023). https://doi.org/10.1038/s41565-023-01038-9

https://www.nature.com/articles/s41565-023-01399-y

2: Ferroelectric memory for back-end-of-line 3D integration. Nat. Rev. Mater. (2023). https://doi.org/10.1038/s41578-023-00578-6

3: A ferroelectric transistor that stores and computes at scale. ScienceDaily (2023). https://www.sciencedaily.com/releases/2023/07/230713141955.htm

4: Radio Frequency Characteristics of InGaAs FE-FETs With Scaled Channel Length. IEEE Trans Electron Devices 70 (2):443–448 (2023). https://doi.org/10.1109/TED.2022.3228971

5: A ferroelectric transistor that stores and computes at scale. ScienceDaily (2023). https://www.sciencedaily.com/releases/2023/07/230713141955.htm

6: Deep Jariwala on Twitter (2021). https://twitter.com/deep29jariwala/status/1384923580123783169

7: Ferroelectric memory for back-end-of-line 3D integration. Nat. Rev. Mater. (2023). https://doi.org/10.1038/s41578-023-00578-6