Mapping 2-Dimensional Algorithms to Hardware with FPGAs

Written by Daniel Hensley, Blayne Kettlewell, Lina A. Colucci, and Sidney Primas at Edge Analytics

CPUs compute along one-dimension: sequentially in time. Algorithms are broken down into instructions that are always loaded and executed one after another. In the future, computation in two-dimensions (2D) will be the norm via hardware (HW) accelerators that support parallel execution over space. This will unify the exploitation of algorithm and HW structure for faster and more efficient solutions.

We’ve seen this trend partially realized with the rise of GPUs that support 2D computation. …

Daniel Hensley

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