Using DFT Architecture for Superior SoC Testing
With advances in technology and shrinking design sizes, power consumption challenges in testing process have grown dramatically. This often makes it (almost) impossible to effectively and accurately test an entire design in the manufacturing stage. A core-based test strategy combined with scan compression is one of the most effective ways to contain huge data volumes and as well as high power consumption of complex SoC tests.
Current Challenges
Traditional scan-based test techniques are not up to the mark, considering how complex SoC designs challenges have become. Design engineers are often plagued by a number of challenges during SoC testing and verification. Some of them include:
• The drop in chip size has caused an overwhelming swell in the number of automatic test pattern generation (ATPG) and in the number of shift cycles per ATPG.
• On top of that, adding delay testing to the scan architecture further multiplies the number of ATPG patterns, putting additional demands on automatic test equipment (ATE) memory.
• Lower geometry design and tremendous switching of ATGP patterns leads to increased power consumption during testing.
• While high dynamic power can burn the device, soaring instantaneous power can lead to excessive IR drop and ultimately device failure.
SoC designs bring with them some other challenges such as:
• Deeply embedded cores
• Complex mixing technologies
• Several analog components
• Multiple hardware description levels for cores
• Various SOC test developers
• Core/test reuse
• IP protection
DFT Architecture
A DFT approach helps overcome the challenges of high power consumption and huge data volume generated during testing.
• DFT offers a power-aware test architecture with top-down and bottom-up hierarchical design support.
• It is a key component of SoC testing, enabling concurrent optimization of timing, area, wiring congestion, and power.
• By partitioning the design into small cores, engineers can test each core independently based on the available I/Os for test and reduce test costs while improving test quality.
• DFT architecture addresses and optimizes multiple design and manufacturing objectives (including timing, area and power) or today’s complex SoCs.
• It offers a single environment for developing high-quality power-aware test architectures that do away with design iterations and eventually reduce cost.
• The single environment with superior rule checking, structure verification, coverage optimization and analysis ensures the highest quality netlist with an advanced test infrastructure.
• Test engineers can create, insert, and hierarchically connect, and verify test structures according to user specification.
• DFT is very easy to deploy and accelerates the development of a higher-quality test infrastructure at lower cost.
• The coverage optimization methodology ensures the highest fault coverage using highly efficient pattern sets.
• High-throughput testing is enabled through the use of compression, ensuring lower costs
• The advanced built-in technology enables test for analog/mixed-signal designs with limited digital inputs.
Benefits
DFT architecture offers engineers a number of benefits:
- DFT accelerates development of a higher quality SoC test infrastructure for defect testing
• It performs concurrent logic and synthesis across several critical parameters such as area, timing, and power
• DFT boosts productivity by bringing test decisions, structure verification, and analysis to the front end
• DFT performs automatic SoC test infrastructure insertion and verification from a single specification and environment and supports hierarchical and flat design flows
• Power-aware DFT inserts validate and tests all power modes, eliminating costly iterations
• Such test coverage optimization enables early analysis that helps engineers improve test pattern volume and test coverage
• DFT optimizes memory test development time and reduces project costs
• Flexible compression architectures dramatically reduce manufacturing test cost, increase throughput, and optimize diagnostic flow, and offers engineers the flexibility in meeting test time
• Advanced masking features ensure the highest compression while maintaining full scan coverage
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