The global market of 3D ICs was valued at US$ 7,521.4 Mn in 2019 and is forecasted to reach a value of US$ 38,252.9 Mn by 2027 at a CAGR of 22.5% between 2020 and 2027.

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The basic definition for 3D ICs is logic over the logic that is connected through TSV. This includes a 3D memory i.e. a memory in the hybrid chip, which has the combined elements of 2.5D with 3D ICs. 3D IC technology can simulate a passive layout structure such as transmission lines and inductors. It also helps in creating high performing, low power consumption microchips.

In the networking industry, high-performance devices require a large storage capacity and bandwidth. In order to maintain these memory and bandwidth challenges, 3D ICs are considered as the ideal solution because, with 3D integration technology, the semiconductor industry gets the high bandwidth benefits and chip density offering. …

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ASIC design

This blog describes the antenna effect observed in the 16nm node design and the way to identify antenna violations in chip(ASIC/FPGA) design using different PV tool. It also described three different methods to fix the violations.

1. Introduction

Effect of charge accumulation in isolated nodes of an integrated circuit during its processing is known as Antenna effect. This effect is also known as Plasma Induced Damage. The discharging of accumulated charges, which is done through the thin gate oxide of the transistor, it might cause damage to the transistors and degrade its performance. During the fabrication process, we need to etch out the unwanted oxide layer from the wafer, which can be done using plasma etching. Plasma contains high energetic ions and radicals for etching that get collected by interconnect. The amount of charge accumulation depends on the surface area of interconnects. These collected ions increase the potential of interconnects and if the interconnect is connected to gate, a drainage path could be formed through the gate oxide to balance out the charge collection depending upon the amount of charge collected by interconnects. The drainage path could either breakdown the gate oxide, which may lead to permanent damage of the device. …

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Silicon Engineering Services

The most disruptive megatrends impacting the ASIC networking industry today include the Internet of Things (IoT), Cloud, and 4G/5G networks. All the industry experts agree that from 2020 to 2025, tens of billions of connected devices will be collecting data and sending it across the software-defined networking (SDN) to ASIC based networking system.

Today, we are in an era of anywhere any device connectivity, and anytime computing, including applications for households, industrial systems, security cameras, baby monitoring, healthcare, wearables, cars, and so much more. …

There can be multiple reasons that can block the test cases to be executed, it might be due to the test environment is not ready or there is a failure somewhere else that stops us getting to execute the test case. What is the blocking item here is C based flow — For processor hex code is required and we generate it using C file whereas IP level verification is generally based on SV-UVM. But is it too easy to reuse IP level test cases at the SoC level design? …

1. What is the physical design in VLSI industry?

In VLSI, physical design (is also known as integrated circuit layout) is a process in which the front end design transfer the structural netlist to the back end design team to convert into a physical layout database which consists of geometrical design information for all the physical layers which is used for interconnections.

2. What is DRC?

DRC is a process where the entire physical design database is checked against design rules. The design layout must adhere to the standards defined by the foundry for manufacturability. DRC was introduced as the lower geometry design technology has evolved vigorously. …

In this era of pervasive connectivity, everything needs to communicate with each other and everything around them by means of the internet. There is never-ending demand for advanced integrated communication in different industry verticals such as Automotive, Consumer Electronics, IT and Telecom. And, it is getting difficult to meet an exponentially growing demand for moving data, faster than ever.

Growing demand of high-speed, low latency applications

A lot of computing process is required to be done at a higher speed with a significant amount of storage requirement, in ML (Machine Learning) and AI (Artificial intelligence) chip design applications.

Telecom operators are trying to cross the line ahead of their competitors in the race of 5G by updating their architecture to support more users, higher data rates, and more data streams per base station. Smart city solutions, Video streaming/AR/VR applications, and automotive applications like ADAS & autonomous vehicles, etc. all demand more bandwidth, lower latencies, and higher speeds as well. Hence the SoCs (System on Chips) are required to be more efficient (energy consumption) and smaller (silicon area). …

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With the advent of personal computers and integrated circuits, the target has been to fit as many transistors as possible in one chip and make them run at the highest possible frequency. A lot of effort has gone in meeting computing scale and performance requirements, from personal computers to data servers, essentially sidelining power optimization or reduction in holistic ways — although it has been constantly considered in implementation flows.

For the last couple of years, the demand for portable devices has increased rapidly; as a result, the semiconductor industry needs to be limit the power consumption of chips. The ASIC/FPGA chip design industry is driven towards low power development due to the widespread use of devices, which require minimal power consumption and maximum speed, such as 4G/5G smartphones, healthcare devices that generate data continuously, smart wearables, and other edge computing devices. …

Design for Testability (DFT), is one of the effective ways to overcome power consumption challenges and huge data volumes in the testing process after production, which has grown dramatically in lower geometry node designs. DFT is becoming a key factor that saves higher design cost, higher power consumption, increasing execution testing time, chip area, pin counts, and other new fault types at small geometries in the testing phase itself.

DFT architecture approach is very easy to deploy, and also accelerates the development of a higher-quality test infrastructure at a lower cost. The advanced built-in technology enables testability for analog and mixed-signal designs with limited digital inputs. …

Verification is the process of reviewing, inspecting, or testing hardware design in order to get the desired output. The whole process revolves around one question: is the spec matching the implementation? This question needs to be asked throughout the verification process.

Structure of verification process
The very basic structure of any verification process is as follows:

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Consider the case of RISC-V (pronounced ‘Risk-Five’). One can’t deny that RISC-V is a strong contender and has huge industry support, for instance, RISC-V events are attracting more exhibitors. …


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