[RISC-V] Learning Note 1 (8/11/19)
Nov 8 · 1 min read
Reference
Summary
Andes offers two new IP cores and one new tool
Two new IP cores
N22 and 25 IP: firm extensions instructions and configurable multipliers; targeted for DSP device
One new tool
ACE (Andes Custom Extension)
“ACE lets designers design their own CPU instructions on the already performance optimised processors”
design CPU specifically for targeted applications; eliminate software bottlenecks and improve run-time performance
Comment
I think ACE is great for the RISC-V community to develop AIoT devices and make the industry more versatile and diversified.
