AsicVault Hardware Wallet Architecture
High Level System Architecture
The AsicVault hardware wallet is a highly integrated miniature device. It keeps private keys, passwords, certificates and other sensitive information in its own internal secure storage inside the secure chip. In addition to secure storage the device features high performance hardware cryptography accelerators for signing and validation of cryptocurrency transactions, blockchain blocks and also encryption/decryption of user data. These accelerators are not available on other common secure element chips.
The central element of AsicVault hardware wallet is the secure chip which features unique security and anti-tamper technologies. The number of external components is tried to keep at minimum to yield high integration and miniature size of the device.
Power management and active antitamper functionalities are provided by very low power FRAM microcontroller (MCU) that can run approximately 30–60 days on the supercapacitor power without recharging. MCU monitors the power of all redundant supercapacitors independently, various properties of anti-tamper meshes and several environmental changes such as light levels, temperature and magnetic field for intrusion prevention purposes. Upon detecting any intrusion attempts the device enters self-destruct mode. Within microseconds all secrets are erased and depending on the predefined user choice, the device is zeroized into like-new state or totally bricked.
Other major external components used in the system are AMOLED touchscreen, 64MB LPDDR memory, 128MB SPI Flash memory, HID-Class USB 2.0 to UART bridge and PCI Express Gen2 to USB3.1 Gen1 controller. LPDDR and SPI Flash are used by the application processor exclusively, they don’t store any security processor code or data. The content of SPI Flash is encrypted and hardware DMA engine with crypto and hashing support is provided to quickly copy data into LPDDR memory. Total amount of application memory in AsicVault devices is 250–500 times larger than what Trezor and Ledger provide. This is ample amount to support numerous cryptocurrencies, tokens and many applications at the same time.
The device is powered by and communicates via USB Type-C connector. Important cryptographic functions, mainly 2 million rounds of PBKDF2-SHA512 and Elliptic Curve operations, are performed without using any external power. During these operations, the device uses power stored in internal supercapacitors, making it impossible to monitor the device power consumption and to perform differential power analysis (DPA). In addition, AsicVault secure chip itself also uses licensed DPA countermeasures.
Several security considerations have also been followed while designing the PCB: only fine-pitch BGA packages for main chips, signals in internal layers only, ground on top/bottom layers, secondary mesh PCB covering all important component areas.
AsicVault hardware design files are available at GitHub and additional information about the hardware wallet can be found on the website.
Secure Chip Architecture
The functionality of AsicVault secure chip is partitioned into two domains — secure domain and application domain. Both domains have their own dedicated CPU to run domain specific code. All externally accessible interfaces are logically connected to the application CPU which does not run security critical or sensitive operations. The application CPU does not have physical access to memories or accelerator components dealing with sensitive data such as passwords, private keys, etc. All communication from application domain to secure domain happens through messages via hardware mailbox component.
The secure CPU is responsible of bringing up the system, running housekeeping/hypervisor functions and processing sensitive information.
AsicVault secure chip incorporates Application Processor (APP CPU), Cryptocurrency Secure Element and GPU on a single chip. Our Cryptocurrency Secure Element consists of Security Processor (SEC CPU), Crypto Accelerators, SECDED SRAM and ROM, embedded encrypted NVM, Secure Key Storage, TRNG and chip level Antitamper Unit. Crypto Accelerators are specifically designed to take into account all different cryptocurrency needs. Only SEC CPU can access Crypto Accelerators, Secure Key Storage and other Secure Element functions.
Application processor and Security processor
Application processor and Security processor are both based on the same RISC-V open instruction set hardware, but they are totally isolated from each other.
Application processor communicates with the outside world using USB2.0 and optional USB3.0 over PCIe interfaces. There is a so-called hardware firewall between the two processors. Only a mailbox with dedicated internal memory is used for APP CPU and SEC CPU communication. Application processor is designed to run untrusted code. It can execute various cryptocurrency wallets, trading applications, password managers, HDD full disk crypto, Bitcoin full node (SPV) software and other user applications.
Both processors have physically totally separate memory subsystems. APP CPU executes code from external LPDDR RAM. SEC CPU has dedicated on-chip read-only memory for code, internal SECDED SRAM for data and a small internal invisible (execute-only) BOOT & SYSTEM ROM.
Certain Secure Element functions are only accessible via SYSTEM ROM that provides additional security layer for: TRNG, Secure Key Storage, Physically Unclonable Function, Encrypted NVM.
SEC CPU incorporates (inside the CPU hardware logic) address protection, code can only be executed from limited address range inside SECDED ROM or BOOT/SYSTEM ROM. BOOT and SYSTEM ROM also have entry point protection.
APP CPU LPDDR memory region protection is managed by the MMU controlled by the SEC CPU. APP CPU can access GPU directly only when this access has been enabled by the SEC CPU.
Crypto accelerators
SHA-512 Unit performs 2 million rounds of PBKDF2 SHA-512 in just a few seconds
ECCCOP, Elliptic Curve Crypto co-processor consists of a 260-bit Multiply and Arithmetic Unit running microcode from a separate embedded RAM. It provides constant time operation to avoid DPA and side channel attacks. It performs 256-bit multiplication followed by 512-bit module prime approximately 500–1000 times faster than Trezor T. Pipelined design of the unit allows even further performance boost of 2–4 times when executing multiple operations in parallel.
PRIME-512, Modulo Prime Unit. It performs 512-bit modulo operation using 256-bit secp256k and other predefined prime numbers in just 5 clock cycles. At 100MHz it means 20 million modulo operations per second.
