Hritvik TanejaRISC vs. CISC Debate on Contemporary ARM and x86 ArchitecturesThe content of this blog is based on the paper Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86…Apr 8, 2019Apr 8, 2019
Hritvik TanejaSimultaneous MultithreadingThe content of the blog is based on the paper Simultaneous Multithreading: Maximizing On-Chip Parallelism.Apr 2, 2019Apr 2, 2019
Hritvik TanejaImproving Memory Scheduling via Processor-Side Load Criticality InformationThe content of this blog is based on the paper: Improving Memory Scheduling via Processor-Side Load Criticality Information.Mar 26, 2019Mar 26, 2019
Hritvik TanejaConcurrent-Refresh-Aware DRAM Memory ArchitectureThe content of this blog is based on the paper CREAM: a Concurrent-Refresh-Aware DRAM Memory Architecture.Mar 19, 2019Mar 19, 2019
Hritvik TanejaTranslation-Triggered PrefetchingThe content of this blog is based on the paper by Abhishek Bhattacharjee. [ http://www.cs.yale.edu/homes/abhishek/abhishek-asplos17.pdf ]Mar 11, 2019Mar 11, 2019
Hritvik TanejaTwo-Way Skewed-Associative CachesIn this blog, we talk about skewed-associative caches. An N-way set associative cache has N banks for an address A and each bank is…Mar 4, 2019Mar 4, 2019
Hritvik TanejaTen Advanced Optimizations of Cache PerformanceThis blog talks about 10 different optimizations for caches and the content of this blog is based on the book Computer Architecture - A…Feb 25, 2019Feb 25, 2019
Hritvik TanejaAdaptive insertion Policies for High-Performance CachingThis blog is written as a part of the course “Computer Architecture” and this blog is based on the paperFeb 13, 2019Feb 13, 2019
Hritvik TanejaValue Prediction in the Multi/Many-core EraValue Prediction (VP) is a microarchitectural technique that speculatively breaks the serialization constraints imposed by true data…Feb 4, 2019Feb 4, 2019
