Design 16-bit CPU by Verilog — Overview

This is Overview of the project that design 16-bit pipeline CPU by verilog.

• Road Map

1. Design Single-Cycle CPU
2. Design Multi-Cycle CPU
3. Design Pipeline

To design single-cycle CPU, must design smaller modules like register file, arithmetic logic unit, etc. So I will design small modules first and integrate it and finally make the single-cycle CPU.

Next, change somthing to upgrade from single-cycle to multi-cycle and pipeline.

• Single Cycle CPU

• Multi Cycle CPU

• Pipeline CPU

To be continued…