[BIOS]GPIO & P2SB

路
1 min readMar 26, 2020

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— — — — — — — P2SB — — — — — — — — — — — —

SPEC (ID:546955 Page:104)

STEP1

Device31 Function1 =0x000F90

+

PCIE base address: 0E000 0000h

=E00F9000

STEP2

P2SB control -offset E0h

在E00F90E0

將bit 8: Hide Device 設為0

才可看到P2SB

STEP3

3.1.6Sideband Register Access BAR (SBREG_BAR) — Offset 10h

在E00F9010

查詢得 0xFD00 0000

— — — — — — — GPIO — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — -

SPEC(ID:546955 Page:1185)

Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0) — Offset 400h

BIt 10-> Pad Mode bit 0 (PMODE0) 設為0= GPIO control

Bit 9 -> GPIO RX Disable (GPIORXDIS)設為1= GPO

Bit 8- > GPIO TX Disable (GPIOTXDIS)設為1= GPI

(Bit 8,9設為1=Disable)

Bit 0 -> GPIO TX State (GPIOTXSTATE) 設為0= LOW , 設為1= HIGH

Example

– GPP_C_12 address

(SBREG_BAR + PortID+ Register Offset)

0xFD00 0000 + 0x00AE 0000 + (0x400 + 12 * 8)

= 0xFDAE0460

AMI GPIO programing

•Community0: PID= 0xAF

– GPP_A & GPP_B

•Community1: PID= 0xAE

– LP: GPP_C & GPP_D & GPP_E

– H : GPP_C & GPP_D & GPP_E & GPP_F & GPP_G & GPP_H

•Community2: PID= 0xAD

– GPD

•Community3: PID= 0xAC

– LP: GPP_F & GPP_G

NOTE

GPI(HW控制)

GPO(BIOS可調控)

- TX is about 3.2V

- RX is 0V

- The RX is the input then it is high impedance.

- The TX is the serial Output and by default is set to mark.

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