PinnedTsungyu LiuHow Engineers Design ChipsAs an Electrical and Computer Engineering student, it is important to know how engineers design a chip. This is my first Medium post, Let…Jul 17Jul 17
Tsungyu LiuIn-Order vs. Out-of-Order ProcessorIn the world of processor architectures, the way instructions are executed plays a crucial role in determining a processor’s performance…1d ago1d ago
Tsungyu Liu[Intro] — 9 Clock Domain Crossing & FIFO DesignIn digital systems, dealing with multiple clock domains is often unavoidable.4d ago4d ago
Tsungyu Liu[Intro] — 8 Static Timing Analysis STAIn digital design, timing is everything.4d ago4d ago
Tsungyu LiuDD Interview Question — Part 1Q1: When you increase the voltage to a buffer, what happens to the delay?Oct 5Oct 5
Tsungyu LiuInstruction Format, Pipelining, Hazard, and SolutionThis week in my Computer System Architecture class, we delved into the intricate world of pipelining in RISC-V processors, specifically…Oct 4Oct 4
Tsungyu Liu[Intro] — 7 Using Multiple Modules in VerilogLet’s review Full Adder again. Below is the truth table of Full AdderSep 18Sep 18
Tsungyu LiuExploring Zen 5 and Zen 4 Microarchitectures: Dive into Op Cache, Branch Prediction, and MoreThe transition from Zen 4 to Zen 5 in AMD’s Ryzen CPUs marks a significant step forward in performance and efficiency, primarily driven by…Sep 7Sep 7
Tsungyu LiuExplore AMD’s FPGA Families and Adaptive SoC -Zynq-7000 SoCAs FPGA technology continues to grow, AMD has strengthened its position, particularly with its Xilinx Spartan, Artix, Kintex, and Virtex…Sep 4Sep 4
![[Intro] — 9 Clock Domain Crossing & FIFO Design](https://miro.medium.com/v2/resize:fill:160:106/1*3W72C95lk5NiIVJe1Pf2KA.jpeg)
![[Intro] — 9 Clock Domain Crossing & FIFO Design](https://miro.medium.com/v2/resize:fill:320:214/1*3W72C95lk5NiIVJe1Pf2KA.jpeg)
![[Intro] — 8 Static Timing Analysis STA](https://miro.medium.com/v2/resize:fill:160:106/1*wsD8joKs-9IW5FsjJeS4-g.jpeg)
![[Intro] — 8 Static Timing Analysis STA](https://miro.medium.com/v2/resize:fill:320:214/1*wsD8joKs-9IW5FsjJeS4-g.jpeg)
![[Intro] — 7 Using Multiple Modules in Verilog](https://miro.medium.com/v2/resize:fill:160:106/1*v7a9TiSAWhAUgAJHRbkvtw.jpeg)
![[Intro] — 7 Using Multiple Modules in Verilog](https://miro.medium.com/v2/resize:fill:320:214/1*v7a9TiSAWhAUgAJHRbkvtw.jpeg)
![[Intro] -6- Sequential Digital Circuits in Detail](https://miro.medium.com/v2/resize:fill:160:106/1*Se64_XTwBKmLEsF6IifC1A.jpeg)
![[Intro] -6- Sequential Digital Circuits in Detail](https://miro.medium.com/v2/resize:fill:320:214/1*Se64_XTwBKmLEsF6IifC1A.jpeg)
