Phase Locked Loops (PLLs)

We have a reference voltage and a locally generated voltage signal. We have to match the phase of the locally generated to the reference.

We obtain and average an error signal by passing it through a low-pass filter.

This averaged error is passed through a voltage-controlled oscillator. This corrects the phase of the locally generated signal.

Input can be an analog or digital signal.

We use a negative feedback system. If the phase is increasing, we must reduce it.

When we match the phase, frequency is automatically matched.

They are used in communication systems to decode an incoming waveform.

Based on the use, there are 4 types of PLLs.

• Analog or linear PLL (LPLL)
• Digital PLL (DPLL)
• All digital PLL (ADPLL)
• Software PLL (SPLL)

LPLL equation

Loop bandwidth

Loop bandwidth defines how fast it can character the phase difference. It mainly depends on the low-pass filter. Frequency dividers can be used to get a different frequency output than the input.

Higher loop bandwidth reduces the lock-in time. However, larger bandwidth makes the PLL harder to control and jitter/noise will pass through the system.