How does pipelining increase the speed of a RISC-V CPU

What is Pipelining?

Pipelining is a technique used to increase CPU speed by splitting one instruction into several micro-instructions(stages) and executing them simultaneously.
This article is more focused on RISC-V CPU architecture, but this method works in many different cases and not only for CPUs or related topics.

How RISC-V CPU is executing instructions?

There are 50 instructions in RISC-V, split into 6 types. Most instructions require 5 stages to execute

Stages are: Fetch, decode, execute, memory ops, write back.

The CPU executes these stages when the CPU clock changes from 1 to 0 or vice versa.

Fetch:

The instruction is read from RAM and stored in a buffer.

Decode:

The instruction is parsed, instruction type is detected, and operands are fetched from registers.

Execute:

Executing instruction logic (arithmetic or logical operations).

Memory ops:

If instruction needs loading or storing data from RAM,it occurs during this stage.

Write back:

If instruction needs to write result in registers,it occurs during this stage.

Each of this stage need some time to execute.
If we execute them sequentially, we must execute them one by one,
so, the total execution time per instruction will be the sum of all 5 stage times.

In this image cpu clock frequency is 1hz so clock is active for 500 ms and inactive for 500 ms and stages are executing sequentially

But what will happened if instead of executing 1 instruction 5 stage sequentially we will execute many instructions one stages per cycle simultaneously ?
This technique is called pipelining, and it allows multiple instructions to be processed concurrently, with each stage handling a different instruction. This can significantly improve the overall throughput and efficiency of the CPU.

This method is widely used to increase CPU speed and not only for CPU.
But it has some drawback/hazards

For example, sometimes one instruction depends on the result of the previous one, or sometimes two instructions need to use a shared resource.
There are three types of hazards

• Structural hazards: Hardware cannot support certain combinations of instructions (two instructions in the pipeline require the same resource).
• Data hazards: Instruction depends on result of prior instruction still in the pipeline
• Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps).

There are ways to fix these hazards, but I will write about them in a different article.