NAND Memory Organization:
- The package is the memory chip, which contains one or more dies.
- The die is the smallest unit that can independently execute commands and report status.
- Each die contains one or more planes. Identical, concurrent operations can take place on each plane, although with some restrictions.
- Each plane contains a number of blocks, which are the smallest unit that can be erased. Remember that, it’s really important.
- Each block contains a number of pages, which are the smallest unit that can be programmed
![The organizational structure of a NAND flash device. [Micron Technology Inc.]](https://miro.medium.com/v2/resize:fit:1100/format:webp/1*bkWslENoNjuhCXvpAqH9mA.png)
Figure 3: The organizational structure of a NAND flash device. [Micron Technology Inc.]
Erase
In a flash memory device, the erase operation is responsible for changing the state of a cell from “0” to “1” by removing electrons from the floating gate. It is important to note that a single cell cannot be directly changed from “1” to “0”; instead, the erase operation must be performed on a block-by-block basis. This means that before new data can be written to a block (through the programming process), the block must first be erased to ensure that it is empty. It is worth noting that the erase operation typically has a longer latency than the read and program operations, meaning it can take longer to complete. For example, the read, program, and erase latencies for a Micron 8 Gb flash chip are 25 μs, 220 μs, and 1500 μs, respectively. As a result, the erase operation can be a performance bottleneck in NAND flash memories, and various firmware algorithms have been developed to minimize the impact of the long erase latency on overall performance.
Write
Program operation is performed on a a page level. This means that the operation targets a specific page of memory on the drive. When the controller of the SSD requests a program operation on the NAND device, it specifies the chip select (CE) and provides the row address of the page to be targeted. The controller then transfers the data to be programmed to the NAND device and sends a final program command to complete the operation.
It is important to note that a page on an SSD cannot be written to more than once without first performing an erase operation. This is because an erase operation is required to clear the page of any existing data before new data can be written to it. As a result, every time a program operation is performed on a page, it must be preceded by an erase operation. This ensures that the page is ready to accept new data and that the program operation is successful.
It is also important to say that pages need to be written in consecutive order within the block, page number 0 is to be written first followed by page 1 write. Writing out of the sequence is not allowed, as violating this rule aggravates bit error rate. A single block does not need to be written all at once. That is, block can be written with pages from 0 to 11, and later on with pages from 12 to 32, for example. Generally, pages need to be written as a whole at once though some memories support so called ‘partial page programming’, which allows a subpage of 512 bytes + correlated spare area to be written.
The data to be written will be provided by the host or due to firmware internal data management. Firmware first transfers the data from cache to NAND internal cache register, once the data transfer is completed the programming should start, i.e., writing to actual NAND cells.
Read
From the perspective of the NAND chips themselves, the read operation involves activating the appropriate word line to select the desired page of cells, and then reading the data stored in those cells by sensing the voltage levels on the bit lines. The NAND chips are organized into blocks, which are further divided into pages. Each page stores a fixed amount of data, typically 4KB to 16KB (or more), depending on the specific NAND device.
In order to read a specific page, the controller must first locate the block that contains the page and then activate the appropriate word line to select the page within that block. The read operation is typically performed by the SSD’s controller, which uses firmware to manage the communication with the NAND chips and handle the necessary data transfer and error correction. The firmware is responsible for optimizing the read performance by minimizing the number of accesses required and maximizing the data transfer rate.
Program/Erase cycle (P/E cycle)
The Program/Erase (P/E) cycle is a fundamental aspect of NAND flash memory, which is commonly used in SSDs. NAND flash memory works by storing data in cells that are grouped into blocks. Each cell can store a single bit of data, and a group of cells is needed to store a larger amount of data. In order to write new data to a cell, the cell must first be erased, which is done by applying a high voltage to the cell. As we already explained above, this process is known as the erase cycle.
Once the cell has been erased, new data can be written to it using a process called programming, which involves applying a lower voltage to the cell. The process of writing new data to a cell by first erase it and then programming it with new data is known as the P/E cycle. The P/E cycle is a key factor in the endurance of NAND flash memory, as the erase cycle can cause wear on the cells over time. As a result, NAND flash memory has a limited number of P/E cycles that it can withstand before it begins to degrade. This is known as the endurance of the memory.
In order to extend the endurance of NAND flash memory, it is important to minimize the number of P/E cycles that the memory undergoes. One way to do this is to use the TRIM command, which allows the operating system to inform the SSD which data blocks are no longer in use and can be erased. This can reduce the number of P/E cycles by eliminating the need to move invalid data during the garbage collection process, which is an internal SSD housekeeping operation that manages and maintains available storage space.
The number of bits that can be stored in each cell of a NAND flash memory drive can also affect the maximum number of program/erase (P/E) cycles that the drive can support. The table below provides an overview of the different types of NAND cells based on the number of bits they can store:
As the number of bits per cell increases, the number of supported P/E cycles tends to decrease. Single-level cell (SLC) NAND, which can store one bit per cell, generally has the highest endurance, while quad-level cell (QLC) NAND, which can store four bits per cell, has the lowest endurance. It is important to consider the endurance of an SSD when selecting a drive, as a drive with a lower endurance may not be suitable for use cases that involve a high number of P/E cycles.