JuxtaPiton + x86 = Google Summer of Code 2019

In this series of posts, continued from JuxtaPiton: With some x86 goodness!, I will be describing the work done for extending JuxtaPiton’s heterogeneous ISA research platform with the open-source ao486 core. In this iteration of JuxtaPiton, we are trying to augment the infrastructure with the open-source ao486 core which is i486 compatible providing x86 ISA support connected with the OpenSPARC T1’s SPARC V9.

In my previous post, I described how the reads and writes work by:


What is JuxtaPiton?

JuxtaPiton is (to our knowledge) the world’s first open-source, general-purpose, heterogeneous-ISA processor being developed at Princeton’s Parallel Group. It was originally designed by Katie Lim (now of the University of Washington) and now under the supervision of Jonathan Balkind and Prof. David Wentzlaff. It serves as a platform to research about Heterogeneous ISAs and presented the case of OpenSPARC T1 core having SPARC V9 ISA and PICORV32 having RISC-V ISA coupled together in its original publication. Both of these cores had a fully cache coherent, shared memory subsystem enabled by OpenPiton’s P-Mesh cache coherence system. The overall infrastructure of JuxtaPiton…


The “bsg_math” implements a variety of routines that employ the coordinate rotational digital computer (CORDIC) algorithm to compute various mathematical functions. All the designs have a parallel architectural configuration for high throughput and are parameterized to varying degrees to have a full control over the power, area, bit-length of datapath and accuracy of the output. The modules are generated by running a script which takes in the parameters for the various bit-lengths of the CORDIC datapath and generates the System Verilog module file. The CORDIC stage module file, that is instantiated inside the main design file according to the corresponding…


Hi Everybody,
My name is Kunal Gulati and I’m an undergraduate student at BITS Pilani, Hyderabad Campus. I’ve always been interested in the hardware side of things like digital circuits, processor design, computer architecture, etc. It was in my freshman year that I first heard about Google Summer of Code since many people from our college participated in it. Not many organizations deal with hardware-based design and develop in HDLs like Verilog, VHDL, etc.
This year I decided to participate and I was fortunate enough to find FoSSi which had some pretty exciting projects. I contacted Prof. Michael Taylor regarding his…

Kunal Gulati

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