Decoding DRAM Timings : Part I

Hardware experts have long been anticipating demise of DRAMs, yet with latest products like HBM2 and DDR5, this technology still remains a popular choice of leading semiconductor companies in the memory products space. Though there are quite a few emerging non-volatile memory technologies like PCM (phase-change memory), ReRAM (resistive RAM), FRAM (ferroelectric RAM)or MRAM (magnetoresistive RAM), these memory types are still in research or early stages of deployment, and are struggling with limitations on speed, endurance and manufacturing costs.

Though DRAM capacity and cost have continously been scaling, latency of DRAM has remained almost constant. Consequently, in order to maximize utilization from DRAM devices, one has to schedule memory accesses in such a way that minimum latency restrictions to guarantee reliable operation, are hidden well behind actual data transfers through multiple levels of parallelism. In-depth understanding of DRAM timing parameters is crucial to achieve this goal and this series of articles is an attempt in this direction. These articles assume that readers are familiar with DRAM system organization and basic memory access protocols.

DRAM chips use capacitor based cells to store data in form of electrical charge. Storing and retrieving data is essentially moving electrical charge to and from these cells, respectively. Such movement of charge is the source of DRAM latency for the following reasons:
i. For storing (writing) data, charge is injected into the cell through a wire called bitline. To reduce cost-per-bit of, many cells are connected to one bitline. Thus, owing to large resistance and the large capacitance of bitline, the cell experiences a large RC-delay, which increases the time it takes to become fully charged.

ii. To increase capacity, the DRAM cell size has been scaled down aggressively limiting the amount of charge that can be stored in its small capacitor which weakens its ability to drive charge into the bitline, while retrieving the data. As a result, cell cannot charge the bitline quickly.

Here’s a summary of few key timing parameters:

tRCD: Delay in moving data from DRAM cells to sense amplifiers as a part of row activation command (referred to as activate command)

tRAS: The minimum time from the initial issuance of the row access command, till the DRAM cells are ready for a precharge

For reads, tRAS ≥ tRCD+ tCAS +Max( tCCD, data burst duration)

In case of writes, tRAS ≥ tRCD + tCWD +tCCD + tWR

tCAS: Time between column read command and valid data on the data bus. Modern DRAM move data in short and continuous bursts.

tCCD: Number of cycles that must be allowed to elapse between successive column commands, determined by internal burst length of the DRAM device.

tCWD: Delay between issuance of the column-write command and placement of data on the data bus by the memory controller

tWR: The minimum time between the end of a write data burst and the start of a precharge command

tWTR: The minimum time interval between the end of a write data burst and the start of a column-read command. Time taken by the write command to release I/O gating resources.

tRP: Delay to reset the bitlines and the sense amplifiers

tRC: The time interval between accesses to different rows within a same bank

tRC = tRAS + tRP

tRRD: Minimum delay between row activation commands to different banks within a same DRAM device

tRFC: Time between a refresh command and a successive refresh or activate

tFAW : Rolling time window in which maximum of four banks can be activated

tRTRS: Rank to rank switching penalty due to system level data strobe resynchronization

In the next article, we would cover commonly used mechanisms to improve DRAM utilization and efficiency within the existing latency constraints.