AMBA Protocol: APB/AHB/AXI

What is AMBA protocol?

AMBA (Advanced Microcontroller Bus Architecture) is a set of specifications for on-chip communication protocols that are widely used in System-on-Chip (SoC) designs.

The AMBA protocols are developed and licensed by ARM Holdings, which is a company known for designing microprocessors and microcontrollers.

What are the main components of AMBA protocol?

The AMBA protocol consists of three main components:

1. Advanced Peripheral Bus (APB)
2. Advanced High-performance Bus (AHB)
3. Advanced eXtensible Interface (AXI)

What are the difference between all 3 Protocol (AXI, AHB, APB)?

The AMBA protocols — AXI (Advanced eXtensible Interface), AHB (Advanced High-performance Bus), and APB (Advanced Peripheral Bus) — are designed for on-chip communication between different components in a System-on-Chip (SoC).

Here are some key differences between these protocols(Bandwidth, Performance, Features, Power Consumption, Complexity, Application):

Bandwidth:

AXI is the highest bandwidth protocol among the three, providing up to 256-bit data transfers.

AHB provides up to 64-bit data transfers

APB provides up to 32-bit data transfers.

Performance:

AXI is designed for high-performance applications and can support multiple outstanding transactions, allowing for efficient pipelining of data transfers.

AHB is also a high-performance bus, but with a slightly lower performance than AXI.

APB is designed for low-bandwidth, low-power applications.

Features:

AXI provides several advanced features like burst transactions, separate read and write channels, and support for multiple outstanding transactions.

AHB also provides some of these features, but not all.

APB is a simpler protocol and does not have these features.

Power consumption:

AXI and AHB are designed to be power-efficient, but APB is optimized for low-power consumption.

Complexity:

AXI is the most complex protocol among the three, with a higher number of signals and more advanced features.

AHB is less complex than AXI, but more complex than APB, which is the simplest protocol.

Applications:

AXI is suitable for high-performance applications like video processing, networking, and graphics.

AHB is used for mid-range applications like microcontrollers.

APB is used for low-bandwidth applications like sensors and audio codecs.

How many channels are there in AXI, AHB, and APB Protocols?

The AMBA protocols — AXI (Advanced eXtensible Interface), AHB (Advanced High-performance Bus), and APB (Advanced Peripheral Bus) — use different numbers of channels for data transfer.

Here is a summary of the number of channels used by each protocol:

AXI: The AXI protocol uses five independent channels for data transfer. They are:
Write Address channel
Write Data channel
Write Response channel
Read Address channel
Read Data channel

AHB: The AHB protocol uses two independent channels for data transfer. They are:
Address/Data channel
Control channel

APB: The APB protocol uses two independent channels for data transfer. They are:
Address channel
Data channel

In summary,

AXI is the most advanced protocol with the highest number of channels, while AHB and APB are simpler protocols with fewer channels.

The number of channels used by each protocol determines the efficiency, performance, and complexity of the communication between different components in a System-on-Chip (SoC).

ADVANTAGES OF AXI OVER AHB PROTOCOL?

1. AXI has 1 read address channel, 1 write address
   channel, 1 read data channel, 1 write data channel. 1
   write response channel That is all together it has 5
   parallel channels.
   Whereas AHB has 1 address channel, 1 read data
   channel, 1 write data channel.
2. AXI as native support for multiple outstanding
   transactions.
3. AXI supports transaction IDs. The user may issue
   multiple outstanding transactions per transaction ID.
4. User can insert a pipeline register anywhere in the
   path of any of the 5 channels, which helps in timing
   closure and help achieve higher operating frequency.

What do you mean by multiple outstanding transactions? Why is it useful?

Master initiates a transaction and doesn’t wait for it to complete(response to arrive) and initiates another transaction. So the first transaction is an outstanding transaction.

AXI supports multiple outstanding transactions so an AXI master doesn’t have to wait for a transaction to complete to initiate a new one. So the
performance is boosted.

What is the difference between AHB and APB?

AHB is a high-performance bus that is used to connect high-speed modules like CPUs, DMA controllers, and memory controllers.

APB, on the other hand, is a low-power, low-bandwidth bus that is used to connect slower peripherals like UARTs, timers, and GPIOs.

What is the AXI protocol?

The AXI (Advanced eXtensible Interface) protocol is a point-to-point interconnect protocol that is used to connect high-speed components such as processors, memories, and other peripherals in a system-on-chip (SoC) design.

it is high speed, low latency protocol.

It is a widely used protocol in the semiconductor industry, as it provides a high-bandwidth and low-latency interconnect solution.

What are the key features of the AXI protocol?

Separate read and write channels, Support for burst transactions, allowing for efficient data transfer, Support for multiple data widths and transfer sizes.

What is an AXI burst?

An AXI burst is a type of transaction that transfers a sequence of data between two components in a single transaction.

Bursts are used to improve data transfer efficiency.

Explain AXI Architecture.

An address channel carries control information that describes the nature
of the data to be transferred.

The data is transferred between master and slave using either:
. A write data channel to transfer data from the master to the slave. In a
write transaction, the slave uses the write response channel to signal the
completion of the transfer to the master.
. A read data channel to transfer data from the slave to the master.
The AXI protocol:
· permits address information to be issued ahead of the actual data
transfer
· supports multiple outstanding transactions
. supports out-of-order completion of transactions

What is an AXI handshaking signal?

An AXI handshaking signal is a signal used to indicate the status of a transaction between two components using the AXI protocol.

The signals include read data ready, write response, and read response.

Why write has 3 channels and read has 2 channels(AXI)?

write transactions have three channels (write address, write data, and write response) while read transactions have two channels (read address and read data).

write response channel is needed to provide feedback to the master about the success or failure of the write operation.

Why READ has only 2 Channels?

READ operation doesn’t have a response channel because direction both the read data and read response is from slave to master.

With every beat, the slave will send a read response along with the data in read data channel.

What is the MINIMUM and MAXIMUM data bus width supported in AXI?

The data bus width as per spec can be 8,16,32 … ,1024 bits. So the minimum is 8 bits and maximum is 1024 bits

WHY IS WRITE DATA CHANNEL TREATED AS BUFFERED?

Write data channel information is always treated as buffered so that the master can perform write transactions without slave acknowledgment of
previous write transactions.

WHICH CHANNELS ARE EXCLUSIVE TO THE SLAVE?

Write Response and Read data channels.

AS PER AXI TERMINOLOGY DIFFERENTIATE BETWEEN BEAT, BURST AND TRANSACTION?

Transaction — The complete set of required operations
on the AXI bus.
Burst — Required payload data to is transferred.
Beats — Burst can consist of multiple data transfers.

( In AXI terminology, a beat is the smallest data transfer unit, a burst is a sequence of beats, and a transaction includes the entire data transfer operation, including bursts and associated control information. )

CAN A MASTER CAN GIVE WLAST IN MIDDLE OF A BURST TRANSFER?

No, Because early burst termination is not supported.

WHAT IS EASY ADDITION OF REGISTER STAGES TO PROVIDE TIMING CLOSURE?

a register stage can be inserted at almost any point in any channel, at the cost of an additional cycle of latency.

WHAT IS AN INTERCONNECT?

An Interconnect is a component with more than one interface that connects one or more master components to one or more slave components.

WHAT IS CONTROL INFORMATION?

The characteristics of a transaction(read/write) like burst_length, burst_size, burst type, atomic characteristics, etc are called the control information.

What is the difference between AXI4 and AXI5?

AXI4 is the fourth version of the AXI protocol, while AXI5 is the latest version.

AXI5 provides some additional features and improvements over AXI4, such as improved memory-mapped performance, increased data transfer efficiency, and better support for low-latency transactions.

( Low latency transaction in AXI protocol refers to minimizing the time it takes for data to be transferred between components )

Does AXI Support existing AHB and APB Interface?

Yes, it supports.

WHAT ARE THE MAJOR ACTIONS DONE BY INTERCONNECT?

Manages the transactions between the MASTER and SLAVE like Routing, providing responses, buffer.

WHAT IS MEANT BY HIGH LATENCY?

If the AXI slave component is taking more time in responding back to the master for the completion of the transfer then such components are said to be having high initial access latency.

IS THERE ANY CHANCE IS GETTING THE SAME ID WITH DIFFERENT MASTER?

No

DIFFERENCE BETWEEN CHANNEL AND BUS ? IF THEY ARE SAME THEN WHY TWO DIFFERENT NAMES?

The input and output on hardware are set to individual channels. But the bus is just a pathway from and-to somewhere.

WHAT IS THE MEANING OF POINT TO POINT INTERCONNECT?

The connection between two components.

WHAT DOES AXLEN AND AXSIZE REPRESENTS?

The AXSIZE signal denotes how much amount of data in bytes can be accommodated in a single beat of the burst.

AXLEN denotes how many transfers are there in a burst.

WHAT IS THE PURPOSE OF BYTE LANE STROBE ? IS STROBE USED FOR BOTH READ AND WRITE OPERATION?

The strobe signal is used to indicate which bytes of the write data bus are valid for each transfer of data. No, it’s only used in a write operation.

WHAT’S THE PURPOSE OF LAST SIGNAL DURING A TRANSACTION? DOES BOTH READ AND WRITE OPERATION USE IT? IF YES, WHICH CHANNEL IS USED TO SEND THIS SIGNAL?

This signal indicates the last transfer in a write/read burst. Yes, Write data and read data channels are used to send this signal.

EXPLAIN THE BASIC HANDSHAKING MECHANISM IN AXI.

1.The source uses the VALID signal to indicate when valid information is available.
2.The VALID signal must remain asserted, meaning set to high, until the destination accepts the information.
3.The destination indicates when it can accept information using the READY signal. The READY
signal goes from the channel destination to the channel source.
4.This mechanism is not an asynchronous handshake and requires the rising edge of the clock for the handshake to complete.

DOES VALID AND READY SIGNAL HAVE DEPENDENCIES ON EACH OTHER?

No, the initiator and receiver should not wait for the assertion of handshaking signal but after a successful handshake, valid must be deasserted as per spec.

WHEN SHOULD THE VALID SIGNAL GO HIGH AND LOW?

VALID should go high when the initiator has valid information to send. It should go low if there is no valid information and it should go low after a
successful handshake.

WHEN MUST THE SLAVE GIVE WRITE RESPONSE?

Write response is generated after the completion of a write transaction.