InSemi Interview Questions
Round 1
1. Explain about your project.
2. Code coverage or functional coverage.
Code coverage measures how much of the code has been executed by the tests, while functional coverage measures how much of the functionality has been tested.
Code coverage is automatically extracted by the simulator when enabled and Functional coverage is a user defined.
3. How did you work on code coverage?
4. How you covered toggle coverage.
5. Phases in UVM?
✔build phase.
✔Connect phase.
✔End of elaboration phase
✔Start of simulation phase
✔Run phase.
✔Extract phase
✔Check phase.
✔Report phase
✔Final phase
6. Which is parallel phase?
Run phase
7. Which phases are top-down, and which one is bottom up?
Only build phase follows top-down approach. Rest all follows bottom-up approach.
8. Why build phase follow top down approach?
The build_phase () method is part of uvm_component class and is used to construct all the child components from the parent component. Hence, build_phase() is always executed top down.
9. Features of AXI?
✔Separate read and write channels.
✔Support for burst transactions.
✔allowing for efficient data transfer.
✔Support for multiple data widths and transfer sizes.
10. Why does write have 3 channels and read has 2 channels?
write transactions have three channels (write address, write data, and write response) while read transactions have two channels (read address and read data).
write response channel is needed to provide feedback to the master about the success or failure of the write operation.
The write response channel is crucial for confirming the success or failure of the write operation. It provides feedback from the slave to the master, indicating whether the write was successful or not. This is essential for maintaining the integrity of data and ensuring that the master is aware of the outcome of the write operation.
11. Different types of response?
In the AXI protocol, there are two primary response types:
**OKAY**: Indicates a successful data transfer.
**ERROR**: Signifies an error or failure in the data transfer, allowing the master to take appropriate corrective actions.
The response is sent from the slave to the master, ensuring proper communication and error handling.
12. Handshaking between driver and sequence?
In UVM, handshaking between a driver and a sequence is typically achieved using UVM sequences’ `start_item` and `finish_item` methods to initiate and complete data transactions. The driver listens for sequence items using the `get_next_item` method, establishing the communication protocol.
13. Get next item is blocking or non blocking?
The get_next_item() is a blocking call to get the sequence item from the sequencer FIFO for processing by driver. Once the sequence item is processed by driver, it needs to call item_done() to complete the handshake before a new item is requested using get_next_item().
14. Item done is blocking or non blocking?
non blocking
15. Where communication is between driver and sequence? Why we need sequencer in between?
In UVM (Universal Verification Methodology), communication between the driver and sequence occurs through the sequencer, which serves as an intermediate component to control the flow of data and stimulus generation, ensuring a structured and synchronized verification process.
16. Where will start sequence?
start sequence in “run_phase” of the test class or the environment class where you initiate the verification process.
17. What is the flow after we start sequence?
18. How do we start the test?
To start a test in UVM (Universal Verification Methodology), you typically use the `run_test()` function in your testbench code, specifying the test you want to run as an argument. For example: `run_test(“my_test”);`.
19. Who initiated the handshake?
20. Config db why used , where used?
UVM’s `uvm_config_db` is a configuration database used to share and retrieve configuration settings among verification components.
It allows a top-level module to store essential information, like virtual interface pointers, which can be accessed by UVM driver and monitor components for signal interaction within the testbench.
For Example,a top level testbench module can store a virtual interface pointer to the uvm_config_db . Then any uvm_driver or a uvm_monitor components can query the uvm_config_db to get handle to this virtual interface and use it for actually accessing the signals through the interface.
we use set() and get() methods.
set:
uvm_config_db#(virtual adder_if) :: set(null, “uvm_test_top”, “aif”, aif);
get:
if(!uvm_config_db #(virtual adder_if) :: get(this, “”, “aif”, aif))
`uvm_error(“drv”,”Unable to access Interface”);
21. What is virtual interface?
✔A virtual interface is a variable that points to an actual interface.
✔A virtual interface in SystemVerilog and UVM is an abstract interface that can connect to multiple actual interfaces dynamically.
✔It allows the testbench to adapt to different interfaces without modifying the code.
22. Why we need virtual interface?
It is used in classes to provide a connection point to access the signals in an interface through the virtual interface pointer.
Virtual interfaces in SystemVerilog and UVM provide flexibility by allowing dynamic connections to different interfaces, promoting testbench reusability and adaptability to various design configurations.
23. I have variable in test, and I want to get in sequence. Is it possible?
Yes, it’s possible. You can pass variables from the test to a sequence in SystemVerilog and UVM by using the `uvm_config_db` or sequence’s constructor arguments.
24. Top is also not a component in uvm ?
In UVM (Universal Verification Methodology), “top” typically refers to the top-level module of the design under verification and is not considered a UVM component.
25. Difference between TLM and Analysis port?
In UVM, TLM (Transaction-Level Modeling) is a high-level, abstract way of modeling communication, while analysis ports provide a specific mechanism for collecting and processing data within UVM components.
TLM is more general, while Analysis ports are a tool for monitoring and collecting data for analysis.
26. Where analysis port is used?
Analysis ports in UVM are used to facilitate communication between different components in a testbench by passing transaction-level data.
Analysis ports in UVM are used for sending data from one component (e.g., a monitor) to another (e.g., a scoreboard) for analysis and comparison.
27. Can I use TLM port to monitor and scoreboard?
No, TLM (Transaction-Level Modeling) ports are typically used for modeling interactions between components, while analysis ports are designed for monitoring and scoreboard purposes in UVM.
Benefits of using Analysis Port over TLM Port:
- Analysis ports provide built-in features for result recording, aggregation, and reporting, making them more suitable for analysis and reporting tasks within the UVM framework.
- They are specifically tailored for analysis, allowing easier integration with UVM components like scoreboards and coverage collectors.
28. In SV can function called inside task?
Yes.
29. Can a task be called inside function? why?
✔One way to call a task inside a function using fork — join_none
✔if you call a task inside a function and that specific task has some sort of delay execution (event, waits or @ something) then you will be getting errors because you are trying to use delays or sync methods in a function that are illegal (at compile time).
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Round 2
1. Drop objection happened but still some comparisons pending in environment. is UVM have any particular facility? Can I raise objections have raise objections? Is objections raise and drop possible in scoreboard?
2. How you will connect driver to DUT in system verilog?
To connect a driver to a DUT (Design Under Test) in SystemVerilog, you typically use a virtual interface. The driver sends transactions through the virtual interface to the DUT, allowing communication between the driver and the DUT for verification purposes.
3. If I want to delay my run phase what to do? When run phase starts? Run phase called by 10ns delay: not possible?
4. What is the use of factory in system Verilog?
In SystemVerilog, the factory is used to create and manage objects and components dynamically.
It allows users to substitute existing class objects with others, enabling customization of testbenches.
5. Assertion for gated clock: whenever the clock enable is there then only clock should be there
assert property ( @ (posedge clk) disable iff(reset) $rose(clk_en) |-> $rose(clk) ) else $display(“Clock not properly gated by enable!”);
OR
property p1;
@(posedge clk) // Assuming a positive edge-triggered clock
disable iff (reset) // Disable the assertion during reset
$rose(clk_en) |-> $rose(clk);
// Check that clock only rises when clk_enable rises
endproperty
assert (p1) else $display(“Clock not properly gated by enable!”);
6. Reverse assertion, whenever no clock enable is 0, there should not be clock
assert property (disable iff ( !clk_en |-> !clk );
7. How will we connect the monitor to scoreboard in system Verilog?
To connect a monitor to a scoreboard in SystemVerilog, you typically use an mailbox to transmit data from the monitor to the scoreboard. This enables the scoreboard to receive and process transaction data generated by the monitor.
8. Which method is used for analysis port?
The method used for analysis port in UVM (Universal Verification Methodology) is `uvm_analysis_port` .
9. If we have multiple analysis port how we can differentiate write methods? Which write called how we will differentiate?
To differentiate between write methods for multiple analysis ports in SystemVerilog, you can use unique method names or provide distinct arguments for each write method.
This way, you can identify which write method is being called based on the method name or the provided arguments.
10. Code coverage is 100% and functional coverage is not 100%, What is conclusion?
A 100% code coverage indicates that all lines of code executed, but not achieving 100% functional coverage suggests that not all intended functionality or corner cases tested.
11. If functional coverage is 100% and code coverage is not 100%, what is conclusion?
If functional coverage is 100% and code coverage is not 100%, it indicates that all intended functionality is tested, but not all codes are executed, possibility of dead code.
12. All coverpoints are covered but still coverage is not complete? update cover points?
If all coverpoints are covered, but coverage is still incomplete, consider adding cross coverage points or improving functional coverage by expanding test scenarios to capture corner cases and unusual interactions within the design.
13. In design there is a debug port and there are some bits that are not connected in design or not used in design, when we can catch this in verification?
You can catch unused bits in a design through verification by analyzing the coverage report for those bits to identify if they are never toggled or covered during simulation.
14. How many channels are there in AXI, AHB, APB protocols?
The AMBA protocols — AXI (Advanced eXtensible Interface), AHB (Advanced High-performance Bus), and APB (Advanced Peripheral Bus) — use different numbers of channels for data transfer. Here is a summary of the number of channels used by each protocol:
o AXI: The AXI protocol uses five independent channels for data transfer. They are:
§ Write Address channel
§ Write Data channel
§ Write Response channel
§ Read Address channel
§ Read Data channel
o AHB: The AHB protocol uses two independent channels for data transfer. They are:
§ Address/Data channel
§ Control channel
o APB: The APB protocol uses two independent channels for data transfer. They are:
§ Address channel
§ Data channel
In summary, AXI is the most advanced protocol with the highest number of channels, while AHB and APB are simpler protocols with fewer channels. The number of channels used by each protocol determines the efficiency, performance, and complexity of the communication between different components in a System-on-Chip (SoC).
15. There are no dependencies on address and data. If my data reaches before address to slave, what slave does? : wait for address or discard data?
If data reaches the slave before the address, the slave should typically wait for the address to arrive before processing the data to ensure correct synchronization and data integrity.
16. If burst operation is going on and ‘wlast’ is driven in between transfer, how slave will react?
If “wlast” is asserted during a burst operation, it typically indicates the end of the current burst, and the slave will respond accordingly by processing the received data through write response channel and preparing for the next transaction.
there are 4 responses OKAY, EXOKAY, SLVERR, DECERROR.
17. 1st fork join then fork join_any and then fork join_none after that disable fork…. Which fork is killed? If we want to kill particular fork what to do?
fork join_any
18. Dut having 2 input ports and output ports are 3. Input port is fed a packet which has address and length. If address is 00 packet will come from 1st output port, if 01 packet will come from 2nd output port. And if 10 then packet will come from 3rd output port. If 11 then invalid. Give brief “verification plan”.
A verification plan for a DUT (Device Under Test) with 2 input ports and 3 output ports, based on address values, can be summarized as follows:
1. Create test cases with input packets having addresses 00, 01, and 10 to validate the expected routing to the 1st, 2nd, and 3rd output ports, respectively.
2. Ensure that for an address of 11, the DUT correctly identifies this as an invalid case and takes appropriate action, such as dropping the packet.
3. Implement testbench scenarios that cover various packet lengths to verify the DUT’s handling of different packet sizes.
4. Perform stress testing by generating a high volume of packets with random addresses and lengths to assess the DUT’s robustness and reliability under varying conditions.
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Round 3
1. What is the difference between AXI and AHB?
- AXI has 1 read address channel, 1 write address
channel, 1 read data channel, 1 write data channel. 1
write response channel That is all together it has 5
parallel channels.
Whereas AHB has 1 address channel, 1 read data
channel, 1 write data channel. - AXI as native support for multiple outstanding
transactions. - AXI supports transaction IDs. The user may issue
multiple outstanding transactions per transaction ID. - User can insert a pipeline register anywhere in the
path of any of the 5 channels, which helps in timing
closure and help achieve higher operating frequency.
2. Why we need 5 channels?
The AXI protocol uses five independent channels for data transfer.
1. Write Address channel
2. Write Data channel
3. Write Response channel
4. Read Address channel
5. Read Data channel
3. What is the importance of 1 KB boundry?
A 1 KB boundary is crucial for memory alignment, optimizing data access and improving performance in computer systems.
4. What is the 2 cycle response in AHB?
The 2-cycle response in AHB (Advanced High-performance Bus) refers to the protocol’s ability to complete a data transfer operation in two clock cycles.
5. What all signals for basic write transaction?
A basic write transaction involves a signal indicating the request to write data (write enable), the data itself, and the address (where the data should be written).
6. Difference between ‘legth’ and ‘size’ of transfer?
Length refers to the number of elements in a data transfer, while size represents the amount of memory occupied by the transfer.
7. Why we run regression? Steps for regression?
Regression in Design Verification helps ensure that recent changes in a project is not affecting the existing functionalities.
steps include selecting test cases, running them, and comparing results with baseline data.
8. How do you generate coverage?
Generate coverage in Design Verification by systematically testing a diverse set of scenarios to ensure all aspects of the design are exercised.
9. Why we need data encapsulation?
Data encapsulation in Design Verification ensures that the internal details of a module are hidden, promoting abstraction.
10. What is the local and protected?
local/private variable is a variable which is access only within class and doesn’t visible in derived class.
protected variable is a variable which is access only within class but visible in derived class.
11. What are mailboxes and semaphores?
Mailboxes (Inter Proccess Communication)in SystemVerilog are communication mechanisms for passing data/transaction between different processes.
Semaphores are synchronization construct used to control access to shared resources in a multi-process environment.
12. What are the ways to synchronize between 2 processes?
In SystemVerilog, you can synchronize between two processes using constructs like `@`, `wait`, and `fork … join`.
13. What is the need of mod ports and clocking blocks?
modport is a construct used in interface to collect signal and provide the direction to the signal.
clocking block is also used to cllect the signals which are commenly clocked.
14. For sum of 2 numbers c=a+b, what is the direction of modport of driver and monitor?
for the driver is “output” and for the monitor is “input.”
15. Handshake between driver and sequencer in UVM?
In UVM, the handshake between a driver and a sequencer is established through the `get_next_item` and `item_done` methods.
16. How transaction is given to DUT?
once sequence started, the body method in sequence get called and sequence component will define the sequence and sequencer will randomize it and manage the communication between sequence and driver.
sequence component send the request to sequencet further to driver using ‘start_item()’ that sequence component is ready with sequence. then driver will send acknowledgement signal ‘gen_next_item’ to sequencer further to sequence then sequence will randomize the data and send the data to sequencer further to driver using ‘item_done()’ once driver received the data from sequence component then driver send the request signal ‘finish_item()’ which means driver is ready for the next transaction.
sequence -> start_item() and item_done()
driver -> gen_next_item() and finish_item()
17. How the connection between monitor and scoreboard is happens?
moniter observes the communication between driver and DUT and convert that observation into transaction and broadcast that transaction to analysis component i.e. Scoreboard through analysis port.
18. We have TLM then why to use Analysis port required?
Analysis port is able to analysis the transaction level data.
19. Why we need analysis FIFO?
to store the transaction from moniter and access the transaction when it is needed by Scoreboard.
