Memory Module Pinouts
1 is ddr ram and the other is ddr2.ram. Both look very similar and would be hard to tell which is which just by looking at them and why doug suggests taking out a stick of ram already in the machine and checking it against what your trying to install just to make sure they are the same, and of course like Digerati said because of the slot(gap. 200 pin SO-DIMM DDR2 SO-DIMM=Small Outline Dual Inline Memory Module 200 pin SO-DIMM DDR2 Usually found todays notebook computers.
30 pin SIMM pin out
72 pin ECC SIMM pin out
72 pin SIMM pin out
72 pin SO DIMM pin out
144 pin SO DIMM pin out
144 pin SODIMM, EDO pin out
168 pin SDRAM DIMM(Unbuffered) Rear Side pin out
168 pin SDRAM DIMM(Unbuffered) Front-side pin out
168 pin SDRAM DIMM (Buffered) pin out
100 pin Unbuffered DIMM pinout
172 pin MicroDIMM pinout
184 pin Registered DIMM pinout
184 pin Unbuffered DIMM pinout
184 pin RDRAM RIMM pin out
200 pin SODIMM DDR pinout [SO-DIMM]
200 pin SODIMM DDR2 pinout [SO-DIMM]
214 pin Micro DIMM DDR2 pinout
240 pin Registered DIMM DDR2 pinout
240 pin Unbuffered DIMM DDR2 pinout
240 pin FB-DIMM pin out
244 pin Registered Mini-DIMM DDR2 pinout
244 pin Unbuffered Mini-DIMM DDR2 pinout
Note: 30-Pin memory modules which were replaced by 72-Pin memory modules are both obsolete. In fact SIMM memory modules were replaced by DIMM memory modules.
DDR2 SDRAM DIMM 240 pin
Ddr2 Ram 8gb
- DDR: Double Data Rate
- DIMM: Dual Inline Memory Module
- SDRAM: Synchronous Dynamic Random AccessMemory, Synchronous to Positive Clock Edge.
PIN CONFIGURATIONS(Front side / back side)
FrontBackPinSymbol1VREF2VSS3DQ04DQ15VSS6DQS0#7DQS08VSS9DQ210DQ311VSS12DQ813DQ914VSS15DQS1#16DQS117VSS18RESET#19NC20VSS21DQ1022DQ1123VSS24DQ1625DQ1726VSS27DQS2#28DQS229VSS30DQ18
Note: Pin 196 is NC for 512MB, or A13 for 1GB and 2GB; pin 54 isNC for 512MB and 1GB, or BA2 for 2GB.
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Pin Descriptions
Pin numbers may not correlate with symbols; refer to PinAssignment table above for more information.
Pin NumbersSymbolTypeDescription195ODT0InputOn-Die Termination: ODT (registered HIGH) enables terminationresistance internal to the DDR2 SDRAM. When enabled, ODT is onlyapplied to each of the following pins: DQ, DQS, DQS#, RDQS, RDQS#,CB, and DM. The ODT input will be ignored if disabled via the LOADMODE command.185, 186CK0, CK0#InputClock: CK and CK# are differential clock inputs. All addressand control input signals are sampled on the crossing of thepositive edge of CK and negative edge of CK#. Output data (DQs andDQS/DQS#) is referenced to the crossings of CK and CK#.52CKE0InputClock Enable: CKE (registered HIGH) activates and CKE(registered LOW) deactivates clocking circuitry on the DDR2 SDRAM.The specific circuitry that is enabled/disabled is dependent on theDDR2 SDRAM configuration and operating mode. CKE LOW providesPRECHARGE POWER-DOWN and SELF REFRESH operations (all device banksidle), or ACTIVE POWERDOWN (row ACTIVE in any device bank). CKE issynchronous for POWER-DOWN entry, POWER-DOWN exit, output disable,and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESHexit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabledduring POWER-DOWN. Input buffers (excluding CKE) are disabledduring SELF REFRESH. CKE is an SSTL_18 input but will detect aLVCMOS LOW level once VDD is applied during first power-up. AfterVref has become stable during the power on and initializationsequence, it must be maintained for proper operation of the CKEreceiver. For proper self-refresh operation VREF must be maintainedto this input.193S0#InputChip Select: S# enables (registered LOW) and disables(registered HIGH) the command decoder. All commands are masked whenS# is registered HIGH. S# provides for external rank selection onsystems with multiple ranks. S# is considered part of the commandcode.73, 74, 192RAS#, CAS#, WE#InputCommand Inputs: RAS#, CAS#, and WE# (along with S#) define thecommand being entered.54 (2GB), 71, 190BA0, BA1, BA2 (2GB)InputBank Address Inputs: BA0–BA1/BA2 define to which device bankan ACTIVE, READ, WRITE, or PRECHARGE command is being applied.BA0–BA1 define which mode register including MR, EMR, EMR(2), andEMR(3) is loaded during the LOAD MODE command.57, 58, 60, 61, 63, 70, 176, 177, 179, 180, 182, 183, 188, 196(1GB, 2GB)A0–A12 (512MB) A0–A13 (1GB, 2GB)InputAddress Inputs: Provide the row address for ACTIVE commands,and the column address and auto precharge bit (A10) for Read/ Writecommands, to select one location out of the memory array in therespective bank. A10 sampled during a PRECHARGE command determineswhether the PRECHARGE applies to one device bank (A10 LOW, devicebank selected by BA0–BA1/BA2) or all device banks (A10 HIGH). Theaddress inputs also provide the op-code during a LOAD MODEcommand.3, 4, 9, 10, 12, 13, 21, 22, 24, 25, 30, 31, 33, 34, 39, 40,80, 81, 86, 87, 89, 90, 95, 96, 98, 99, 107, 108, 110, 111, 116,117, 122, 123, 128, 129, 131, 132, 140, 141, 143, 144, 149, 150,152, 153, 158, 159, 199, 200, 205, 206, 208, 209, 214, 215, 217,218, 226, 227, 229, 230, 235, 236DQ0–DQ63I/OData Input/Output: Bidirectional data bus.6, 7, 15, 16, 27, 28, 36, 37, 45, 46, 83, 84, 92, 93, 104, 105,113, 114, 126, 135, 147, 156, 165, 203, 212, 224, 233 125, 134,146, 155, 164, 202, 211, 223, 232DQS0–DQS8, DQS0#– DQS17#, DM0–DM8 (DQS9– DQS17)I/OData Strobe: Output with read data, input with write data forsource synchronous operation. Edge-aligned with read data, centeraligned with write data. DQS# is only used when differential datastrobe mode is enabled via the LOAD MODE command. Input Data Mask:DM is an input mask signal for write data. Input data is maskedwhen DM is sampled HIGH along with that input data during a WRITEaccess. DM is sampled on both edges of DQS. Although DM pins areinput-only, the DM loading is designed to match that of DQ and DQSpins. If RDQS is disabled, DQS0–DQS17 become DM0–DM8 andDQS9#–DQS17# are not used.42, 43, 48, 49, 161, 162, 167, 168CB0–CB7I/OCheck Bits.68PAR_INInputParity bit for the address and control bus.55ERR_OUTOutputParity error found on the address and control bus.120SCLInputSerial Clock for Presence-Detect: SCL is used to synchronizethe presence-detect data transfer to and from the module.101, 239, 240SA0–SA2InputPresence-Detect Address Inputs: These pins are used toconfigure the presence-detect device.119SDAI/OSerial Presence-Detect Data: SDA is a bidirectional pin used totransfer addresses and data into and out of the presence-detectportion of the module.18RESET#InputAsynchronously forces all registered outputs LOW when RESET# isLOW. This signal can be used during power up to ensure that CKE isLOW and DQs are High-Z.53, 59, 64, 67, 69, 172, 178, 184, 187, 189, 197,VDDSupplyPower Supply: 1.8V ±0.1V.51, 56, 62, 72, 75, 78, 170, 175, 181, 191, 194,VDDQSupplyDQ Power Supply: 1.8V ±0.1V.1VREFSupplySSTL_18 reference voltage.2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47,50, 65, 66, 79, 82, 85, 88, 91, 94, 97,100, 103, 106, 109,112, 115,118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154,157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219,222, 225, 228, 231, 234, 237VSSSupplyGround.238VDDSPDSupplySerial EEPROM positive power supply: +1.7V to +3.6V.19, 54 (512MB, 1GB), 76, 77, 102, 171, 196 (512MB), 173,174,NC-No Connect: These pins should be left unconnected.137, 138, 220, 221RFU — Reserved for future use.
References
Ddr2 Ram Slot Pinout Adapter
- Micron: DDR2 SDRAM (PDF link)
