Chip Analog Layout — Using AI

Chip Analog Layout — Using AI

Step-1:

Detect different types of “Transistor Pairs”.

Method: We can extract this information from the netlist file. This extraction can be based on a simple rule based extractor.

1.Current Mirror Pairs

2.Differential Pairs

3.CascodePairs

4.Complementary Pairs (Class AB o/p, IO drivers etc.)

5.Collaborator/Co-operative Pairs (current sharing x-tors(20–80 diode and constant current) etc.)

6.LatchupPairs

Step 2:

Detect different types of Metal Lines or Pairs, and corresponding nodes.

Method: We can extract this through a simple Siamese sort of network, which gives a similarity score for any two lines in the netlist. Or train a LLM to postulate line pairs

1.Clock-Signal lines

2.Differential lines

3.Reference lines -Current and Voltage

4.Low RC lines

5.High Frequency vs Low Frequency lines

6.Low noise lines

Step 3:

Extract and Compute various physical indices

Method: From layout simulations or geometrical calculations

1.Sim-2-Sil correlation (Multipliers vs Fingers)

2.Type of Transistors (Multipliers vs Fingers Folding, LOCOS effects, )

3.Matching index (W, L)

4.Orientation and Alignment index (direction on W,L)

a. Fringe Effects (on Channel Length)

5.Symmetry index

a.Inter-digitation

b.Common Centroid

6.Fringe field index (Capacitors)

7.Interconnect Parasitics

a.Line Resistance

b.Line Inductance

c.Line Capacitance (Shielding)

d.Line Conductance (Leakage current into insulators)

8.Electro-migration index

9.Heat and Mechanical stress index (Bandgaps and reference circuits –voltage & clock)

10.ESD & Latchup Indices

Step 4:

Usage and Mechanisms of Indices: Artificial Intelligence in Layout design and layout production

1.Polygon based optimization

a.Every element of layout for a component is represented as a polygon [x,y,w,h]

b.Optimize by adjusting [x,y,w,h]

c.Ex: Mosfet: Gate Poly-[x,y,w,h]

Drain/Source Diff –[x,y,w,h]

2.Simulation based

a.Create indices for each of the components that have to be drawn in the layout.

b.When a given layout is presented, derive the indices

c.Generate a reward based on the indices, with weightages (importance)

Come up with a complex multi dimensional reward function, based on indices

d.Feed these points for layout optimization

3.LLM based

a.Understand the design rules (DRC), methods and techniques and capture the essence of the same

b.When a given layout is presented, specify the rules that are met and the rules that are not met.

c.Generate a reward based on the quality of the rules that are met and that are not met.

d.Feed these points for layout optimization (RL)

Or a

combination of the above three mechanisms.

Architectural Representation of Layout Production using Artificial Intelligence Mechanisms