Life with an FPGA — 2: The “ugly” lights

Prologue

This is the second part of the tutorial on how to code on Xilinx FPGAs using the Vivado Design Suite. If you haven’t read the first one and are a beginner I would strongly recommend to go over that one first.

In this tutorial, I won’t be as elaborate as I was in the first one as I would assume the reader of this tutorial has already gone through the first one. For instance, I will not explain how to create a project again, or how to generate a bitstream.

In the last tutorial the lights were beautiful but now I have the ugly ones for you. When I started programming FPGAs, I did not struggle as much to blink the lights on a pynq board as I did on the Virtex Ultrascale+ (VCU118) board. Thus, the “ugly” lights.

The lights are, however, the same. The only difference is that pynq board had a single-ended clock while the virtex board has a differential clock.

Hardware and software specs used:

Vivado: 2018.1

OS: Ubuntu 18.04

Board: Virtex Ultrascale+ VCU118

Step 1: Create the project by selecting the appropriate board. (Refer to the first tutorial if you have any problems).

Step 2: Add a design source with the following verilog code.

module blink(
input clk_p,
input clk_n,
output led
);
wire clk;
IBUFGDS bufgd_inst(.I(clk_p), .IB(clk_n), .O(clk));

reg [26:0] count_q = 0;

always @(posedge clk) begin
count_q <= count_q+1;
end

assign led = count_q[26];

endmodule

You will notice that there are two clock inputs in this code. It is because of the differential clock. It is basically the two wires of the same signal which will be eventually used to transmit a single signal. The IBUFGDS module basically combines the signal and gives “clk” as an output which is then used as the clock as it was used in the pynq example.

Step 3: The constraint file is the only thing why I created this redundant looking tutorial. It is not redundant. We used the GUI to write the .xdc file or the constraint file last time from the elaborated design. Here we will write the constraint file. We will use the VCU118’s user guide. You can find the constraint file listing on the page 115. We will first look for specifying the clock and then led.

In both the images, I have purposefully left the page numbers so that you can open the book and get an idea. Thus with this constraint list we make two constraint files.

We go to Add Sources -> Add or create constraints -> create file. Write the following code in it.

set_property PACKAGE_PIN AY24 [get_ports clk_p]
set_property IOSTANDARD LVDS [get_ports clk_p]
set_property PACKAGE_PIN AY23 [get_ports clk_n]
set_property IOSTANDARD LVDS [get_ports clk_n]
set_property PACKAGE_PIN AT32 [get_ports led]
set_property IOSTANDARD LVCMOS12 [get_ports led]

Then create another constraint file like above and write the following code.

create_clock -period 8.000 -name clk -waveform {0.000 4.000} [get_ports clk_p]

Therefore, you will have 2 constraint files and 1 design source file. After this the process is the same. Generate the bitstream and program the board like in the previous tutorial.

Cheers to the ugly lights…

Happy Learning!