Hetero Junction Intrinsic Thin Layer solar cell (HIT)

HIT is an acronym for Hetero Junction Intrinsic Thin layer solar cells. It is an excellent example of Bandgap Engineering.

Sanyo (which was then bought by Panasonic) was the first to develop the concept of HIT and has its patent. The IP rights of Sanyo were over in 2010 and since then several companies are working on different designs of HIT, however, the basic concept of HIT remains the same.

There are a few terms that need to be understood for better understanding of HIT -

1. Hetero junction: When the junction of the semiconductor of the different bandgap is formed, it is referred to as heterojunction. In HIT, we use N-type Si and its bandgap is 1.1 eV. This N-type c-Si is sandwiched between two a-Si:H (amorphous Silicon) with a bandgap of 1.7 eV each. The advantage of such a structure is higher bandgap which provides a selective barrier to electrons and holes to cross over to the other side, therefore, it reduces the probability of unwanted recombination of electrons and holes which impacts short-circuit current. Since a-Si:H is of higher bandgap than c-Si, there is no obstruction to light that falls on c-Si. Another advantage is that it provides excellent passivation to c-Si surface. To understand Passivation, recall Si crystal structure! Si is a tetrahedron and holds 4 Si atoms by sharing an electron and making a covalent bond with neighboring Si. Since the Si crystal is lying on the topmost layer, it has nothing to hold on to. Thus open covalent bond becomes a sink for electron or hole and reduces the open-circuit voltage. By depositing a-Si:H layer on the surface, we take care of these ‘open’ bonds which are referred to as passivation. It has a direct impact on open-circuit voltage which is higher in the case of HIT (greater than 0.7 V). Thus, by providing Heterojunction, we took care of passivation as well as barriers to electron and holes.
2. Intrinsic: Intrinsic semiconductors are those which are not doped intentionally. a-Si:H provides effective passivation only if a-Si:H is intrinsic. Thus, surface passivation in n-Si is obtained by depositing an intrinsic layer of a-Si:H.
3. Thin layer: Since the a-Si:H is intrinsic, n and p-type doped a-Si:H are placed over intrinsic a-Si:H layers on both sides (please refer to figure) to get the electrons and holes required for current flow. If these intrinsic layers are thick, electrons and holes will get lost within the layers before reaching to c-Si and therefore they need to be thin and provide easy penetration to reach to n-type c-Si.

An important point to be noted is that a-Si:H processing involves a low thermal budget process as it can be processed around 200℃-300℃. Thus, the entire HIT processing requires a low thermal budget.

In the next blog, I will tell you how electrons and holes are transported in the HIT structure.

Originally published at https://www.linkedin.com.