8x1 Multiplexer (Behavioral) Implementation in Verilog

Now start the journey of a Digital Logic Design System. A multiplexer, often abbreviated as “mux,” is a combinational logic circuit that selects one of several input signals and forwards it to a single output. A set of control signals controls the input signal selection, typically referred to as “select” or “address” lines.The given Verilog code defines a module named “mux_8x1_bh” which implements the functionality of an 8x1multiplexer. Here’s a breakdown of the module:

`timescale 1ns / 1ps

module mux_8x1_bh(
    output reg y,
    input [7:0]i,
 input [2:0]s
    );
    
    always @(*)
    begin
    case(s)
        3'b000:y=i[0];
        3'b001:y=i[1];
        3'b010:y=i[2]; 
        3'b011:y=i[3];
        3'b100:y=i[4];
        3'b101:y=i[5];
        3'b110:y=i[6]; 
        3'b111:y=i[7];
    endcase
    end
endmodule

Explanation:

• This Verilog module represents an 8-to-1 multiplexer (mux), where one of the eight input signals is selected based on a 3-bit select signal.
• The module consists of an output port y, which serves as the output of the multiplexer, and two input ports: i for the 8-bit data inputs and s for the 3-bit select signal.
• Inside the module, there’s a always block sensitive to any changes in its inputs (*). This means the block will execute whenever any of its inputs change.
• Within the always block, a case statement is used to select the appropriate input based on the value of the selected signal s.
• The case the statement covers all possible combinations of the 3-bit select signal (s). For each combination, it assigns the corresponding input (i) to the output (y).
• This module implements the functionality of an 8-to-1 multiplexer using behavioral Verilog without directly instantiating any hardware primitives.

The Verilog module mux_8x1_tb is a testbench designed to verify the functionality of the mux_8x1_bh module, which implements an 8x1 multiplexer. Below is an explanation of the mux_8x1_tb module:

`timescale 1ns / 1ps

// Module definition for the testbench
module mux_8x1_tb;
    // Declaration of signals
    wire y;            // Output of the DUT (Device Under Test)
    reg [7:0] i;       // 8-bit input
    reg [2:0] s;       // 3-bit select signal
    
    // Instantiation of the DUT
    mux_8x1 dut(y, i, s);

    // Initial block for testbench setup
    initial
    begin
        // Initialize inputs
        i = 8'b00000000;  // Initial value for 8-bit input
        s[0] = 0;         // Initial value for select bit 0
        s[1] = 0;         // Initial value for select bit 1
        s[2] = 0;         // Initial value for select bit 2
        
        // Stimulus generation
        #100 i = 8'hca;    // Change input after 100 time units
        #200 i = 8'h0f;    // Change input after 200 time units
        #500 i = 8'h5a;    // Change input after 500 time units
        
        // Finishing simulation after 1500 time units
        #1500 $finish();
    end
    
    // Toggle select signals at different intervals
    always #100 s[0] = ~s[0];  // Toggle select bit 0 every 100 time units
    always #200 s[1] = ~s[1];  // Toggle select bit 1 every 200 time units
    always #400 s[2] = ~s[2];  // Toggle select bit 2 every 400 time units
endmodule

• This Verilog code defines a testbench (mux_8x1_tb) for the 8x1 multiplexer (mux_8x1).
• Inside the testbench, there are signal declarations for the output y, the 8-bit input i, and the 3-bit select signal s.
• The multiplexer (mux_8x1) is instantiated (dut) with the declared signals.
• The initial block (initial) is used for testbench setup. It initializes inputs, generates stimulus, and finishes the simulation after a certain time.
• Inputs i are changed at different time intervals to stimulate the multiplexer.
• The always blocks toggle the select signals s at different intervals to control the selection of inputs in the multiplexer.

RTL Viewer:

RTL Diagram of 8x1multiplexer

Simulation Waveform:

Waveform of 8x1multiplexer