BCD to 7 Segment Decoder Implementation in Verilog

A BCD to 7-segment Decoder is a circuit that converts Binary-Coded Decimal (BCD) inputs into signals that drive a 7-segment display to show numbers. The given Verilog code defines a module named “bcd_7_seg” which implements the functionality of an A BCD to 7-segment Decoder. Here’s a breakdown of the module:

module bcd_7_seg(
  output reg [6:0] seg,
  input [3:0] bcd
);

  always @(*)
  begin
    case (bcd)
      4'b0000: seg = 7'b0000001;
      4'b0001: seg = 7'b1001111;
      4'b0010: seg = 7'b0010010;
      4'b0011: seg = 7'b0000110;
      4'b0100: seg = 7'b1001100;
      4'b0101: seg = 7'b0100100;
      4'b0110: seg = 7'b0100000;
      4'b0111: seg = 7'b0001111;
      4'b1000: seg = 7'b0000000;
      4'b1001: seg = 7'b0000100;
      default: seg = 7'bxxxxxxx;
    endcase
  end
endmodule

Explanation:

• output reg [6:0] seg,: Declares an output port named seg, which is a 7-bit wide vector. The reg keyword indicates that this output is a register.
• input [3:0] bcd: Declares an input port named bcd, which is a 4-bit wide vector.
• always @(*): This indicates a combinational logic block that triggers whenever any of the signals in the sensitivity list (*) changes.
• begin: Marks the beginning of the procedural block.
• case (bcd): Starts a case statement based on the value of the bcd input.
• 4'b0000: seg = 7'b0000001;: If the input bcd is 0000 (decimal 0), it assigns the value 0000001 to the output seg, corresponding to displaying the digit 0 on a 7-segment display, where segments 'a' and 'b' are active.
• Similarly, other cases map the BCD inputs to the corresponding 7-segment display configurations.
• default: seg = 7'bxxxxxxx;: If the input bcd does not match any of the defined cases, it assigns an undefined value to seg, indicated by xxxxxxx.
• endcase: Marks the end of the case statement.
• end: Marks the end of the procedural block.
• endmodule: Marks the end of the module definition.

The Verilog module “bcd_7_seg_tb” is a testbench designed to verify the functionality of the “bcd_7_seg” module, which implements a BCD to 7-segment Decoder. Below is an explanation of the“bcd_7_seg_tb” module:

module bcd_7_seg_tb;

  reg [3:0] bcd;
  wire [6:0] seg;
  bcd_7_seg dut (
    .bcd(bcd),
    .seg(seg)
  );

  initial begin
    bcd = 4'b0000;
    #100 bcd = 4'b0001;
    #100 bcd = 4'b0010;
    #100 bcd = 4'b0011;
    #100 bcd = 4'b0100;
    #100 bcd = 4'b0101;
    #100 bcd = 4'b0110;
    #100 bcd = 4'b0111;
    #100 bcd = 4'b1000; 
    #100 bcd = 4'b1001;
    #100 bcd = 4'b1111; 
    #1000 $finish;
  end
  
endmodule

• reg [3:0] bcd;: Declares a 4-bit wide register named bcd to simulate the BCD input.
• wire [6:0] seg;: Declares a 7-bit wide wire named seg to capture the output of the bcd_7_seg module under test.
• bcd_7_seg dut (: Instantiates the module under test (bcd_7_seg) and connects its ports to the testbench signals.
• .bcd(bcd),: Connects the input port bcd of the DUT to the testbench signal bcd.
• .seg(seg): Connects the output port seg of the DUT to the testbench signal seg.
• initial begin: Marks the beginning of the initial block, which contains the testbench stimulus.
• bcd = 4'b0000;: Sets the initial value of bcd to 0000 (decimal 0).
• #100 bcd = 4'b0001;: After a delay of 100 time units, change the value bcd to 0001 (decimal 1).
• Similarly, the subsequent lines change the value bcd at intervals of 100 time units to test different BCD inputs.
• #1000 $finish;: After a delay of 1000 time units, finish the simulation.
• end: Marks the end of the initial block.
• endmodule: Marks the end of the testbench module definition.

RTL Viewer:

RTL Diagram of BCD to 7-segment Decoder

Simulation Waveform:

Waveform of BCD to 7-segment Decoder