Logic Gates By 2X1 MUX Implementation in Verilog

Now start the journey of a Digital Logic Design System. This Verilog module implements various logic gates using 2x1 multiplexers (MUX). Each MUX takes two inputs and selects one of them based on the control input. Here’s a breakdown of the gates implemented:

module logic_gates_by_2x1mux(
    input a,
    input b,
    output y1,y2,y3,y4,y5
);
   
 // Define 2X1 MUX instances for each logic gate
 
 // AND gate implementation
 mux_2x1 and_gate(1'b0, b, a, y1); // Selects 'b' when control input is 0, 'a' when it's 1 (AND gate)
 
 // NAND gate implementation
 mux_2x1 nand_gate(1'b1, ~b, a, y2); // Selects complement of 'b' when control input is 1, 'a' when it's 0 (NAND gate)
 
 // OR gate implementation
 mux_2x1 or_gate(b, 1'b1, a, y3); // Selects 'b' when control input is 0, 'a' when it's 1 (OR gate)
 
 // NOR gate implementation
 mux_2x1 nor_gate(~b, 1'b0, a, y4); // Selects complement of 'b' when control input is 0, 'a' when it's 1 (NOR gate)
  
 // XOR gate implementation
 mux_2x1 xor_gate(a, ~a, b, y5); // Selects 'a' when control input is 0, complement of 'a' when it's 1 (XOR gate)

endmodule


module mux_2x1(
    input a, b, sel, 
    output y);
    // MUX functionality: y = (a & ~sel) | (b & sel)
    // When sel is 0, output y selects input a; when sel is 1, output y selects input b.
    assign y = (a & ~sel) | (b & sel);
endmodule

Explanation:

This Verilog module, named “logic_gates_by_2x1mux”, implements five different two-input logic gates: AND, OR, XOR, NAND, and NOR.

• AND Gate (y1)
• OR Gate (y2)
• XOR Gate (y3)
• NAND Gate (y4)
• NOR Gate (y5)

These gates are implemented using the assign statement, which directly assigns values to the output ports based on the logic operations performed on the input ports.

This Top module can be instantiated in mux_2x1 modules to perform logic operations on signals a and b according to the specified gates.

The Verilog module “logic_gates_by_2x1mux_tb” is a testbench designed to verify the functionality of the “logic_gates_by_2x1mux” module, which implements logic gates logic. Below is an explanation of the logic_gates_by_2x1mux_tb module:

module logic_gates_by_2x1mux_tb;
    reg a, b; // Declare input registers for signals a and b
    wire y1, y2, y3, y4, y5; // Declare output wires for the logic gates
    
    logic_gates_by_2x1mux uut(a, b, y1, y2, y3, y4, y5); // Instantiate the DUT (Design Under Test)
    
    // Initial block for stimulus generation
    initial begin
        a = 0; b = 0; // Set initial values for inputs a and b
        #100; // Wait for 100 time units
        
        a = 0; b = 1; // Change input values
        #100; // Wait for 100 time units
        
        a = 1; b = 0; // Change input values
        #100; // Wait for 100 time units
        
        a = 1; b = 1; // Change input values
        #100; // Wait for 100 time units
        
        $finish; // Terminate simulation
    end
    
    // Initial block for monitoring and displaying signals
    initial $monitor("a=%b b=%b y1=%b y2=%b y3=%b y4=%b y5=%b", a, b, y1, y2, y3, y4, y5);
    
endmodule

This testbench module (logic_gates_by_2x1mux_tb) is used to verify the functionality of the logic_gates_by_2x1mux module. It stimulates the inputs a and b with different values and monitors the outputs y1, y2, y3, y4, and y5. The $monitor statement displays the values of these signals whenever they change.

RTL Viewer:

RTL Diagram of logic_gates_by_2x1mux

Simulation Waveform:

Waveform of logic_gates_by_2x1mux