How a CPU Works: The 16-bit x86 Bus Cycle

Ah, the Intel x86 architecture. This is the CPU architecture that has powered consumer computing for almost 40 years.

The 16-bit 8086 was released in 1978 and was the first 16-bit CPU by Intel. Based on a 3um process, the CPU had a 40 pin DIP packaging and was clocked between 5 MHz and 10 MHz.

The 8086 CPU

The specifications of the 8086 CPU included a 20-bit address bus, 16-bit data bus along with 16-bit general purpose registers. What made the 8086 interesting at the time was that it was produced when most home microcomputers were still 8-bit. And thus, many were only able to address up to 64 KB of memory.

With the 20-bit address bus, the 8086 was capable of addressing up to 1024 KB, or 1 MB of memory. This CPU was then made the IBM PC attractive and was one of the main marketing points when the IBM PC was released. A microcomputer touting memory expandability at a time when computers were advancing quickly made it all the better investment for a family to purchase.

We can easily talk about the specifications, history and other interesting trivia about the 8086, but that’s not what this article is for. I believe that sort of information can easily be found online. The purpose of this discussion is to dive a bit more technically into the intricacies of the CPU: how it is driven, how it processes an instruction, how it communicates with devices within the motherboard, and so on.

So let’s begin and take a trip on the x86 “bus”.

How does the CPU Move?

How does the x86 execute one instruction after another on its own once we have turned on the computer?

When I was 4-years old, my family had bought a 486-class home computer. Being the first time I had ever seen such an object, I asked my mom if there was a little person inside the box pulling wires and making things appear on the screen.

The answer I would tell my 4-year old self would be: No, there is no little person inside the box fiddling with wires when you’re using the computer.

The answer I would give myself in this present day is that it is all driven through electricity. Wait, isn’t that obvious?

The beauty of electricity is that it travels very fast — in the order of nano-seconds. When we pulsate electrical signals on and off at a high frequency, we can create the illusion of something that is constantly on. Note this is similar to how a lightbulb depending on where you live, can switch on and off anywhere from 50 times (50 Hz) to 60 times (60 Hz) per second.

The same concept can be applied for the CPU. In the 286 CPU, there was an input pin called CLK that would receive a signal generated by an external crystal oscillator. The external crystal oscillator would be connected to the CPU through this CLK pin.

The crystal oscillator in this context, is essentially a physical electrical tuning fork that pulsates at a high frequency. This crystal oscillator is connected by a power source on the motherboard. On its own, if voltage is applied to the crystal oscillator, it begins to vibrate at its set frequency. The vibrations will cause the electrical signals to be generated to its output pin which is then passed as an input signal to the CPU’s CLK pin.

The oscillator does this repeatedly and then drives the CPU to operate at a pace that can be thought of as a metronome. This frequency controlled by the oscillator is a base frequency and can then be divided, or multiplied up to get an effective CPU frequency. Keep in mind that the CPU still also receives power on its own.

For example, in the Intel 80286 (286), the CLK signal was actually divided by 2 because transistors at the time could not operate that fast. Suppose a crystal oscillator operated at 40 MHz and was connected to a 286. The 286 would receive this frequency from the oscillator through the CLK pin and would divide this signal by 2. This would cause the CPU to run effectively at 20 MHz. This effective frequency is referred to as the PCLK.

Precise timing is essential to the CPU. The CPU must allow itself time to correctly perform communications with certain devices connected onto the motherboard, or memory at very sensitive time intervals. These crucial operations are grouped into what we refer to as the “bus cycle”.

The Bus Cycle

We can now think of the CPU having a heartbeat driven by the crystal oscillator — providing it electrical signals every period of time at a high frequency.

When a CPU begins to receive electrical signals, it waits for the signal from the power supply called the POWERGOOD signal. Note, when the power is initially turned on, your computer does not immediately send power to the CPU as the power that is supplied needs to be clean and in a stable state before anything happens. Otherwise, things could potentially fry.

When this POWERGOOD signal is asserted onto the CPU, the CPU will begin what is called the BUS CYCLE that will then drive the fetch-decode-execute loop. Internally, the CPU has what we call a BUS UNIT that serves as the entry point to the outside world. The BUS UNIT effectively is the only component of the 16 bit x86 CPU that has contact to the “outside world”.

The BUS UNIT contains a set of lines to communicate with external components. They are: the address bus, the data bus and the control bus. Specifically, the address bus allows the CPU to communicate with memory. The data bus allows the CPU to read and write data to memory and the external devices. Finally, the control bus is the set of lines that will tell the CPU what type of operation the current BUS CYCLE is intended for.

When the 16 bit x86 initially powers on, the first address the CPU reads is hardwired to a specific value. For the 286, the 24 bit address is 0xFFFFF0, and for the 8086/8088, the address is 0xFFFF0. This address is usually located in non-volatile memory. This is almost always going to be the boot ROM in the PC case. The boot ROM can also be synonymous with the BIOS. This boot ROM will then cause the CPU to execute a series of instructions which will then eventually load programs such as the operating system and allow for other programs for the CPU to execute.

But how does it do that? Let’s remember that instructions are essentially a series of math operations along with memory reads and writes. A BUS CYCLE is simply the communication process between some sort of memory in the system to and from the CPU. It is helpful to always look at communication from the CPU perspective. They say the world does revolve around the CPU, right?

The BUS UNIT makes use of a state machine to drive a BUS CYCLE. This state machine goes through 3 phases:

  1. Address Time
  2. Data Time
  3. Optional Wait Time

The transition is as follows: Address Time → Data Time. During address time, the CPU will evaluate an address for 1 state which is defined to be a specific number of nanoseconds. The bits composing the address will be sent to the lines in the address bus to be moved. The state machine then transitions to data time. During this transition, a series of signals will then be set in the control bus to indicate whether or not we want to:

  1. Read data from memory or an I/O device.
  2. Write data to memory or an I/O device.

During data time, the state machine will transfer the data from/to (depending on the control bus settings) RAM or the I/O device. The caveat is that Ww are still limited by physics in that certain devices will take a longer period of time to actually physically latch onto the bits that are sent from the CPU to store into the device’s memory.

To resolve this, an extra state/time is made available for the state machine to transition to. This is called the wait/ready state. This period of time can be named Wait Time. When the state machine transitions into wait time, machine will wait for 1 state until the device signals that it is READY. If the device is not ready, then the state machine will continue to stay in its wait time. Once the device is ready, the state machine within the bus unit will complete the bus cycle and again, transition back to address time to read in the next address. The CPU will wait as necessary for the device to finish its current memory or data operation.

Now suppose the CPU is receiving data from data time. During the receiving period where the CPU is reading in an instruction to perform execution, we go through the decoding process of this instruction to see what operation is needed to perform from the BUS UNIT. This unit that controls this is conveniently named: DECODE UNIT. The decoding unit will figure out what to do and will pass the data to the EXECUTION UNIT to process that piece of data.

The point to be made here is that the bus cycle always performs in the pair of address time to data time transition one memory address at a time (while waiting as necessary). Repeat this process over and over again and we basically have the main component that makes the fetch-decode-execute loop possible.

So, that’s how the bus cycle helps the CPU actually communicate with memory to actually get things done.

Okay, so now what do all the 0s and 1s mean when the CPU grabs this from the bus cycle? How does it know how to decode the stream of 0s and 1s? We’ll go in more detail how the decode unit works next time. :)

Resource: ISA System Architecture. 3rd Edition. Don Anderson and Tom Shanley. 1995