A List of Chip/IP for Deep Learning
After reading the article “FPGAs and AI processors: DNN and CNN for all” by Matt Hurd , I think it is a right time to make a list of chips and IPs for Deep Learning. So I built one on GitHub, and will keep updating it.
- Nvidia’s latest GPU can do 15 TFlops of SP or 120 TFlops with its new Tensor core architecture which is a FP16 multiply and FP32 accumulate or add to suit ML.
- Nvidia is packing up 8 boards into their DGX-1for 960 Tensor TFlops.
- Nvidia Volta — 架构看点 gives some insights of Volta architecture.
- On edge, Nvidia provide NVIDIA DRIVE™ PX, The AI Car Computer for Autonomous Driving and JETSON TX1/TX2 MODULE “The embedded platform for autonomous everything”
Open Source DLA from Nvidia
- Nvidia anouced “XAVIER DLA NOW OPEN SOURCE” on GTC2017. We did not see Early Access verion yet. Hopefully, the general release will be avaliable on Sep. as promised. For more analysis, you may want to read 从Nvidia开源深度学习加速器说起.
- The soon to be released AMD Radeon Instinct MI25 is promising 12.3 TFlops of SP or 24.6 TFlops of FP16. If your calculations are amenable to Nvidia’s Tensors, then AMD can’t compete. Nvidia also does twice the bandwidth with 900GB/s versus AMD’s 484 GB/s.
AMD has put a very good X86 server processor into the market for the first time in nine years, and it also has a matching GPU that gives its OEM and ODM partners a credible alternative for HPC and AI workload to the combination of Intel Xeons and Nvidia Teslas that dominate hybrid computing these days.
- Intel purchased Nervana Systems who was developing both a GPU/software approach in addition to their Nervana Engine ASIC. Comparable performance is unclear. Intel is also planning in integrating into the Phi platform via a Knights Crest project. NextPlatform suggested the 2017 target on 28nm may be 55 TOPS/s for some width of OP. There is a NervanaCon Intel has scheduled for December, so perhaps we’ll see the first fruits then.
Mobileye is currently developing its fifth generation SoC, the EyeQ®5, to act as the vision central computer performing sensor fusion for Fully Autonomous Driving (Level 5) vehicles that will hit the road in 2020. To meet power consumption and performance targets, EyeQ® SoCs are designed in most advanced VLSI process technology nodes — down to 7nm FinFET in the 5th generation.
- Movidius VPU is basicly an array of vector processor.
This DLU that Fujitsu is creating is done from scratch, and it is not based on either the Sparc or ARM instruction set and, in fact, it has its own instruction set and a new data format specifically for deep learning, which were created from scratch.
Japanese computing giant Fujitsu. Which knows a thing or two about making a very efficient and highly scalable system for HPC workloads, as evidenced by the K supercomputer, does not believe that the HPC and AI architectures will converge. Rather, the company is banking on the fact that these architectures will diverge and will require very specialized functions.
- Google’s original TPU had a big lead over GPUs and helped power DeepMind’s AlphaGo victory over Lee Sedol in a Go tournament. The original 700MHz TPU is described as having 95 TFlops for 8-bit calculations or 23 TFlops for 16-bit whilst drawing only 40W. This was much faster than GPUs on release but is now slower than Nvidia’s V100, but not on a per W basis. The new TPU2 is referred to as a TPU device with four chips and can do around 180 TFlops. Each chip’s performance has been doubled to 45 TFlops for 16-bits. You can see the gap to Nvidia’s V100 is closing. You can’t buy a TPU or TPU2. Google is making them available for use in their cloud with TPU pods containing 64 devices for up to 11.5 PetaFlops of performance.
Other references are:
Xilinx provide “Machine Learning Inference Solutions from Edge to Cloud” and naturally claim their FPGA’s are best for INT8 with one of their white papers.
Whilst performance per Watt is impressive for FPGAs, the vendors’ larger chips have long had earth shatteringly high chip prices for the larger chips. Finding a balance between price and capability is the main challenge with the FPGAs.
- Microsoft has thrown its hat into the FPGA ring, “Microsoft Goes All in for FPGAs to Build Out AI Cloud.”
- Wired did a nice story on the MSFT use of FPGAs too, “Microsoft Bets Its Future on a Reprogrammable Computer Chip”
- Inside the Microsoft FPGA-based configurable cloud is also a good reference if want to know Microsoft’s vision on FPGA in cloud.
Qualcomm has been fussing around ML for a while with the Zeroth SDK and Snapdragon Neural Processing Engine. The NPE certainly works reasonably well on the Hexagon DSP that Qualcomm use. The Hexagon DSP is far from a very wide parallel platform and it has been confirmed by Yann LeCun that Qualcomm and Facebook are working together on a better way in Wired’s “The Race To Build An AI Chip For Everything Just Got Real”, “And more recently, Qualcomm has started building chips specifically for executing neural networks, according to LeCun, who is familiar with Qualcomm’s plans because Facebook is helping the chip maker develop technologies related to machine learning. Qualcomm vice president of technology Jeff Gehlhaar confirms the project. “We’re very far along in our prototyping and development,” he says.” Perhaps we’ll see something soon beyond the Kryo CPU, Adreno GPU, Hexagon DSP, and Hexagon Vector Extensions. It is going to be hard to be a start-up in this space if you’re competing against Qualcomm’s machine learning.
In a recent blog, “We are making on-device AI ubiquitous” shows its AI road map.
Will it or won’t it? Bloomberg is reporting it will as a secondary processor but there is little detail. Not only is it an important area for Apple, but it helps avoid and compete with Qualcomm.
Core ML is Apple’s current sulotion for machine learning application.
DynamIQ is embedded IP giant’s answer to AI age. It may not be a revolutionary design but is important for sure.
ARM also provide a open source Compute Library contains a comprehensive collection of software functions implemented for the Arm Cortex-A family of CPU processors and the Arm Mali family of GPUs.
It is a manycore processor network on a chip design, with 4096 cores, each one simulating 256 programmable silicon “neurons” for a total of just over a million neurons. In turn, each neuron has 256 programmable “synapses” that convey the signals between them. Hence, the total number of programmable synapses is just over 268 million (228). In terms of basic building blocks, its transistor count is 5.4 billion. Since memory, computation, and communication are handled in each of the 4096 neurosynaptic cores, TrueNorth circumvents the von-Neumann-architecture bottlenecks and is very energy-efficient, consuming 70 milliwatts, about 1/10,000th the power density of conventional microprocessors. Wikipedia
Yu Chengdong, Huawei CEO, recently announced at the 2017 China Internet Conference that Huawei is developing an AI processor.
Kirin for Smart Phone
Kirin 970 may have an embedded deep learning accelerator.
Mobile Camera SoC
According to a Brief Data Sheet of Hi3559A V100ESultra-HD Mobile Camera SoC, it has:
Dual-core CNN@700 MHz neural network acceleration engine
Cambricon is working on IP License, Chip Service, Smart Card and Intelligent Platform.
Cambricon just raised record $100M round A.
Chinese startup Horizon Robotics joined forces with Intel to showcase an Advanced Driver Assistance System (ADAS) at CES 2017 which is a single camera that can see stuff and identify it. They also teamed up with Midea and launched an intelligent air conditioner that no doubt solves loads of first world problems including home security. No news yet on when we can expect their Brain Processing Unit (BPU) to debut but it was supposed to be “in early 2017“. The founder and CEO of Horizon Robotics, Dr. Kai YU, used to be the Head of Baidu Institute of Deep Learning so we’re expecting some great things from this startup which has taken in an undisclosed amount of funding so far.
DeePhi Tech has the cutting-edge technologies in deep compression, compiling toolchain, deep learning processing unit (DPU) design, FPGA development, and system-level optimization. This nextplatform arcicle FPGA Startup Gathers Funding Force for Merged Hyperscale Inference gave more information of the company.
Bitcoin Mining Giant Bitmain is developing processors for both training and inference tasks.
Wave’s Compute Appliance is capable to run TensorFlow at 2.9 PetaOPS/sec on their 3RU appliance. Wave refers to their processors at DPUs and an appliance has 16 DPUs. Wave uses processing elements it calls Coarse Grained Reconfigurable Arrays (CGRAs). It is unclear what bit width the 2.9 PetaOPS/s is referring to. Some details can be fund in their white paper.
Some more details can be fund in this article: AI芯片 浅析Yann LeCun提到的两款Dataflow Chip
Graphcore raised $30M of Series-A late last year to support the development of their Intelligence Processing Unit, or IPU. Resently, co-founder and Chief Technology Officer, Simon Knowles, was invited to give a talk at the 3rd Research and Applied AI Summit (RAAIS) in London, showing interesting ideas behind their processor.
解密又一个xPU：Graphcore的IPU give some analysis on its IPU architecture.
PEZY Computing K.K.
Pezy-SC and Pezy-SC2 are the 1024 core and 2048 core processors that Pezy develop. The Pezy-SC 1024 core chip powered the top 3 systems on the Green500 list of supercomputers back in 2015. The Pezy-SC2 is the follow up chip that is meant to be delivered by now, but details are scarce yet intriguing,
“PEZY-SC2 HPC Brick: 32 of PEZY-SC2 module card with 64GB DDR4 DIMM (2.1 PetaFLOPS (DP) in single tank with 6.4Tb/s” It will be interesting to see what 2,048 MIMD MIPS Warrior 64-bit cores can do. In the June 2017 Green500 list, a Nvidia P100 system took the number one spot and there is a Pezy-SC2 system at number 7. So the chip seems alive but details are thin on the ground. Motoaki Saito is certainly worth watching.
Their product page has since June 2016 gone missing in action. Not sure what they are up to with the $100M they put into their MIMD architecture. It was described at the time as having 256 tiny DSP, or tDSP, cores on each ASIC along with an ARM controller suitable for sparse matrix processing in a 35W envelope.
The performance is unknown, but they compared their chip to a current NVIDIA, at that time, and said they had 2.5 times the performance. We know Nvidia is now more than ten times faster with their Tensor cores so KnuEdge will have a tough job keeping up. A MIMD or DSP approach will have to execute awfully well to take some share in this space.
Since KnuEdge “emerged from stealth” last year, the company has gone quiet and not offered up any additional information about what they’ve been up to. According to an article in VentureBeat, we know that KnuEdge has already been generating revenue and that they were considering raising more funding this year in addition to the $100 million in “patient money” they have already raised. Their website contains next to no information aside from employee profiles. At an Xconomy conference a few weeks ago, the Company talked about “cloud-based machine intelligence as a service” that is “supposed to be rolled out sometime this year“.
Tenstorrent is a small Canadian start-up in Toronto claiming an order of magnitude improvement in efficiency for deep learning, like most. No real public details but they’re are on the Cognitive 300 list.
Thinci is developing vision processors from Sacremento with employees in India too. They claim to be at the point of first silicon, Thinci-tc500, along with benchmarking and winning of customers already happening. Apart from “doing everything in parallel” we have little to go on.
Founded in 2010, Eldorado Hills, California startup ThinCI has taken in an undisclosed amount of funding to develop a technology that will bring vision processing to all devices. The ability for smart devices to have functionality like computer vision that doesn’t require regular communication to the cloud is referred to as “edge computing” or “fog computing”. That’s where ThinCI wants to play.
Koniku’s web site is counting down to “your new reality”. They have raised very little money and after watching their Youtube clip embedded in this Forbes page, you too will not likely not be convinced, but you never know. Harnessing biological cells is certainly different. It sounds like a science project, but, then this,
“We are a business. We are not a science project,” Agabi, who is scheduled to speak at the Pioneers Festival in Vienna, next week, says, “There are demands that silicon cannot offer today, that we can offer with our systems.” The core of the Koniku offer is the so-called neuron-shell, inside which the startup says it can control how neurons communicate with each other, combined with a patent-pending electrode which allows to read and write information inside the neurons. All this packed in a device as large as an iPad, which they hope to reduce to the size of a nickel by 2018.
Adapteva: “Adapteva tapes out Epiphany-V: A 1024-core 64-bit RISC processor.” Andreas Olofsson taped out his 1024 core chip late last year and we await news of its performance. Epiphany-V has new instructions for deep learning and we’ll have to see if this memory-controller-less design with 64MB of on-chip memory will have appropriate scalability. The impressive efficiency of Andrea’s design and build may make this a chip we can all actually afford, so let’s hope it performs well.
- Knowm is actually setup as a .ORG but they appear to be pursuing a for-profit enterprise. The New Mexcio startup has taken in an undisclosed amount of seed funding so far to develop a new computational framework called AHaH Computing (Anti-Hebbian and Hebbian). The gory details can be found in this publication, but the short story is that this technology aims to reduce the size and power consumption of intelligent machine learning applications by up to 9 orders of magnitude.
A battery powered neural chip from Mythic with 50x lower power.
Founded in 2012, Texas-based startup Mythic (formerly known as Isocline) has taken in $9.5 million in funding with Draper Fisher Jurvetson as the lead investor. Prior to receiving any funding, the startup has taken in $2.5 million in grants. Mythic is developing an AI chip that “puts desktop GPU compute capabilities and deep neural networks onto a button-sized chip — with 50x higher battery life and far more data processing capabilities than competitors“. Essentially, that means you can give voice control and computer vision to any device locally without needing cloud connectivity.
Despite many promises,Kalray has not progressed their chip offering beyond the 256 core beast covered back in 2015, “Kalray — new product meander.” Kalray is advertising their product as suitable for embedded self-driving car applications. Kalray has a Kalray Neural Network (KaNN) software package and claims better efficiency than GPUs with up to 1 TFlop/s on chip. Kalrays NN fortunes may improve with an imminent product refresh and just this month Kalray completed a new funding that raised $26M. The new Coolidge processor is due in mid-2018 with 80 or 160 cores along with 80 or 160 co-processors optimised for vision and deep learning.
Brainchip’s Spiking Neuron Adaptive Processor (SNAP) will not do deep learning and is a curiosity without being a practical drop in CNN engineering solution, yet. IBM’s stochastic phase-change neurons seem more interesting if that is a path you wish to tread.
Groq is founded by Ex-googlers, who designed Google TPU.
Speaking of chips, AImotive and partner VeriSilicon are in the process of designing a 22 nm FD-SOI test chip, which is forecast to come out of GlobalFoundries’ fab in Q1 2018 (Figure 4). It will feature a 1 TMAC/sec aiWare core, consuming approximately 25 mm2 of silicon area; a Vivante VIP8000-derivative processor core will inhabit the other half of the die, and between 2–4 GBytes of DDR4 SDRAM will also be included in the multi-die package. The convolution-tailored LAM in this test chip, according to Feher, will have the following specifications (based on preliminary synthesis results): 2,048 8x8 MACs Logic area (including input/output buffering logic, LAM control and MACs): 3.45mm2 Memory (on-chip buffer): in the range of 5–25mm2 depending on configuration (10–50 Mbits).
Another interesting activity of Aimotive is Neural Network Exchange Format (NNEF).
Deep Vision is bulding low-power chips for deep learning. Perhaps one of these papers by the founders have clues, “Convolution Engine: Balancing Efficiency & Flexibility in Specialized Computing”  and “Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing” .
We are carrying out research on original chip architectures in order to implement Neural Networks on a circuit enabling low power DeepLearning
This crowdfunding effort made its way into our original article on AI chips so it’s only fair we include it in this one. While it is not actually possible to pick a worse name for your startup than “krtkl”, at least the product name is manageable. Snickerdoodle is “reconfigurable hardware for building intelligent systems” (think Raspberry Pi). A crowdfunding effort for Snickerdoodle raised $224,876 and they’re currenty shipping. If you pre-order one, they’ll deliver it by summer. The palm-sized unit uses the Zynq “System on Chip” (SoC) from Xilinix.
TeraDeep is building an AI Appliance using its deep learning FPGA’s acceleration. The company claims image recognition performance on AlexNet to achieve a 2X performance advantage compared with large GPUs, while consuming 5X less power. When compared to Intel’s Xeon processor, TeraDeep’s Accel technology delivers 10X the performance while consuming 5X less power.
Synopsys Embedded Vision
- VeriSilicon’s Vivante VIP8000 Neural Network Processor IP Delivers Over 3 Tera MACs Per Second