Understanding SPI

The Serial Peripheral Interface (SPI) is a commonly utilized interface bus for the exchange of data between microcontrollers and small peripherals, including shift registers, sensors, displays, and flash memory. Unlike asynchronous communication methods like I2C and UART, SPI employs synchronous communication, utilizing distinct clock and data lines.

An notable advantage of SPI lies in its ability to transfer data seamlessly without interruption. Unlike I2C and UART, which send data in packets with predefined bit limits and distinct start and stop conditions, SPI facilitates the continuous transmission of any number of bits.

In SPI communication, devices operate within a master-slave framework, where the master, typically a microcontroller, controls the communication, and the slave, such as a sensor, display, or memory chip, follows instructions from the master.

Master — slave communication

1. MOSI (Master Out Slave In) — Send the data from the master to the slave device
2. MISO (Master In Slave Out) — Receive the data from the slave to the master
3. SCLK (Serial Clock) — Clock that is generated by master
4. SS/CS/CE (Salve Select/Chip Select/Chip Enable) — To select the slave device in the SPI bus interface.

Synchronization

The clock serves as an oscillating signal dictating precisely when the receiver should sample the bits present on the data line. This sampling occurs at either the rising edge (transition from low to high) or falling edge (transition from high to low) of the clock signal, as indicated in the datasheet. When the receiver detects that edge, it will immediately look at the data line to read the next bit

https://www.teachmemicro.com/spi-primer/

Slave Select (SS)

The master has the capability to designate the specific slave with which it intends to communicate by lowering the slave’s CS/SS line to a low voltage level. In the idle, non-transmitting state, the slave select line is kept at a high voltage level.

The master may feature multiple CS/SS pins, enabling the parallel wiring of several slaves. In cases where only one CS/SS pin is available, multiple slaves can still be connected to the master through a daisy-chain logic.

SPI Modes

The timing of data transmission in relation to the clock pulse is crucial. There are four distinct approaches to achieving this, giving rise to four distinct “SPI modes”. Apart from determining the clock frequency, the master is also required to configure the clock polarity (CPOL) and clock phase (CPHA) in relation to the data.

These two parameters, CPOL and CPHA, are used to form four unique modes to provide flexibility in communication between master and slave.

SPI Modes

https://www.mikroe.com/blog/spi-bus

MULTIPLE SLAVES

SPI can be configured to function with a single master and a single slave, or it can be configured to accommodate multiple slaves under the control of a single master. When connecting multiple slaves to a master, there are two methods.

If the master has multiple slave select pins

If the master has only one slave select pin

Daisy Chaining

Advantages of SPI protocol

• SPI supports high data transfer rates, making it suitable for applications that require fast communication between devices.
• SPI is relatively simple and straightforward to implement compared to other communication protocols, which makes it a popular choice for many embedded systems.
• SPI allows full-duplex communication, enabling simultaneous data transmission and reception.
• SPI does not involve master arbitration during communication, which means that any device on the bus can communicate with any other device as long as the timing is synchronized.

Disadvantages of SPI protocol

• SPI is typically designed for short-distance communication within a single PCB or between closely located devices. It may not be the best choice for applications that require long-distance communication.
• Unlike protocols such as I2C, SPI does not have a standardized specification, which can lead to variations in implementation between different manufacturers.
• SPI typically requires four wires (clock, MOSI, MISO, and select), which may be considered a disadvantage in applications where minimizing the number of wires is critical.
• SPI operates in a master-slave configuration, and the master device controls the communication. If the master device fails, the entire communication bus may be affected.